A special-purpose interface circuit for a computer hard-disk drive (HDD) enables rapid writing of image data from a scientific instrument to sequential sectors on the hard disk. The design of this interface exploits the fact that most of the hardware and software components typically used to control the flow of data to the HDD of a general-purpose personal computer (PC) are not needed in a special-purpose instrument application; as a result, the size, weight, and power consumption of the data-storage portion of the instrument can be made less than they would be if a general-purpose interface were used. This interface can be connected directly to any of a variety of commercially available HDDs.

The Interface Circuit enables rapid writing of source data to sequential sectors on a hard disk. The interface circuit can be connected directly to any of a variety of commercially available HDDs.

In the original application for which the interface was designed, the image data originate in a charge-coupled-device (CCD) camera that generates 12 bits per pixel, there being 3,072 pixels per line and 1,024 lines per image frame. Image data are read out from the CCD at a rate of 11.4Mb/s. Header information that is included with the data from each line increases the data rate to 15.2Mb/s. The HDD must be capable of accepting data at this rate to store complete images.

The interface (see figure) includes a serial-to-parallel converter, a first-in/first-out (FIFO) buffer, and a custom interface control unit. The serial-to-parallel converter and the interface control unit are implemented on a field-programmable gate array (FPGA). The FPGA contains instructions in read-only memory (ROM) that initialize the HDD by use of an industry-standard interface protocol called "ATA-3." For each image line, the starting sector address is written to the HDD control registers. All of the source data (image data) pass through the serial-to-parallel converter, then through the FIFO buffer. The FIFO buffer can store several image lines simultaneously, making it possible for the control unit to wait while the HDD seeks the desired sector addresses.

After a complete line has been written, the control unit determines the status of the HDD and waits until the HDD is ready to receive more data. When the HDD is ready, it accepts header information, then accepts the source data. During acceptance of the source data, 16-bit words are written from the FIFO buffer to sequential HDD sectors at a system clock rate of 10 MHz. Later, stored data are retrieved from the hard disk by use of a separate commercial parallel input/output PC card.

Going beyond the original application, this interface can be used in other applications in which it is necessary to write data on sequential hard-disk sectors at high speeds. Because the interface includes an FPGA, it can be modified to satisfy requirements of different applications.

This work was done by Joseph Miko of Goddard Space Flight Center. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp  under the Electronics & Computers category. GSC-14177

NASA Tech Briefs Magazine

This article first appeared in the February, 2000 issue of NASA Tech Briefs Magazine.

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