Arrays of CdZnTe photodetectors and associated electronic circuitry have been built and tested in a continuing effort to develop focal-plane image sensor systems for hard-x-ray telescopes. Each array contains 24 by 44 pixels at a pitch of 498 µm. The detector designs are optimized to obtain low power demand with high spectral resolution in the photon-energy range of 5 to 100 keV.
More precisely, each detector array is a hybrid of a CdZnTe photodetector array and an application-specific integrated circuit (ASIC) containing an array of amplifiers in the same pixel pattern as that of the detectors. The array is fabricated on a single crystal of CdZnTe having dimensions of 23.6 by 12.9 by 2 mm. The detector-array cathode is a monolithic platinum contact. On the anode plane, the contact metal is patterned into the aforementioned pixel array, surrounded by a guard ring that is 1 mm wide on three sides and is 0.1 mm wide on the fourth side so that two such detector arrays can be placed side-by-side to form a roughly square sensor area with minimal dead area between them.
Figure 1 shows two anode patterns. One pattern features larger pixel anode contacts, with a 30-µm gap between them. The other pattern features smaller pixel anode contacts plus a contact for a shaping electrode in the form of a grid that separates all the pixels. In operation, the grid is held at a potential intermediate between the cathode and anode potentials to steer electric charges toward the anode in order to reduce the loss of charges in the interanode gaps.
The CdZnTe photodetector array is mechanically and electrically connected to the ASIC (see Figure 2), either by use of indium bump bonds or by use of conductive epoxy bumps on the CdZnTe array joined to gold bumps on the ASIC. Hence, the output of each pixel detector is fed to its own amplifier chain. In the ASIC, each pixel contains a preamplifier, a shaping amplifier, a discriminator, and sampling and pulsing circuits. All the pixels share a serial readout line. The ASIC has been designed to operate with low noise and to consume no more than about 50 mW of power in normal operation.
The ASIC is controlled by a microprocessor — a 24-bit minimum-instruction-set computer (MISC) implemented on a field-programmable gate array. The MISC runs on a 7.3728-MHz clock cycle that is established by an oscillator that runs at a frequency of 14.7456-MHz. Three static random-access memory (SRAM) circuits provide a total of 128 kB of 24-bit memory. The output of the ASIC readout line is fed to a 12-bit analog-to-digital converter (ADC) that consumes 80 mW of power. The MISC then feeds the output of the ADC to a level shifter that, in turn, transmits the digital output to an external computer via a serial data line.
The sensor system consumes 700 mW of power. By careful design of the ASIC and off-chip digital signal processing, it has been possible to achieve energy resolution less than 1 keV for hard x-rays at an operating temperature of 0 °C.
This work was done by C. M. Hubert Chen, Walter R. Cook, Fiona A. Harrison, Jiao Y. Y. Lin, Peter H. Mao, and Stephen M. Schindler of the California Institute of Technology for Goddard Space Flight Center. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/Computers category. This invention is owned by NASA, and a patent application has been filed. Inquiries concerning nonexclusive or exclusive license for its commercial development should be addressed to the Patent Counsel, Goddard Space Flight Center, (301) 286-7351. Refer to GSC- 14804-1.