Modifications have been made in the design of instruments of the type described in “Digital Averaging Phasemeter for Heterodyne Interferometry” (NPO-30866), NASA Tech Briefs, Vol. 28, No. 9 (September 2004), page 6a. To recapitulate: A phasemeter of this type measures the difference between the phases of the unknown and reference heterodyne signals in a heterodyne laser interferometer. This phasemeter performs well enough to enable interferometric measurements of displacements with accuracy of the order of 100 pm. This is a single, integral system capable of performing three major functions that, heretofore, have been performed by separate systems: (1) measurement of the fractional-cycle phase difference, (2) counting of multiple cycles of phase change, and (3) averaging of phase measurements over multiple cycles for improved resolution. This phasemeter also offers the advantage of making repeated measurements at a high rate: the phase is measured on every heterodyne cycle. Thus, for example, in measuring the relative phase of two signals having a heterodyne frequency of 10 kHz, the phasemeter would accumulate 10,000 measurements per second. At this high measurement rate, an accurate average phase determination can be made more quickly than is possible at a lower rate.
At the time of writing the cited prior article, the phasemeter design lacked immunity to drift of the heterodyne frequency, was bandwidth-limited by computer bus architectures then in use, and was resolution-limited by the nature of field-programmable gate arrays (FPGAs) then available. The modifications have overcome these limitations and have afforded additional improvements in accuracy, speed, and modularity.
The modifications are summarized as follows:
- Taking advantage of improvements made in FPGAs since the original design effort, major phasemeter functions are implemented in a commercial, off-the-shelf FPGA card. It is necessary to add supplementary interface electronic circuitry to support legacy peripheral equipment, but even so, it is significantly easier to implement the phasemeter in the modified design than in the original high-speed-digital-board design.
- In the previous design, a reference clock signal having a frequency of 128 MHz was generated outside the FPGA and delivered to the FPGA board via a coaxial cable. Since many commercial FPGAs contain built-in phase-locked-loop frequency multipliers, it has become feasible to utilize these multipliers to internally generate a reference clock signal in response to a precise externally generated reference signal having a frequency between 10 and 20 MHz. In addition, the internally generated reference clock signal has a higher frequency — 200 MHz — and, hence, affords higher resolution.
- Modularity is enhanced by incorporation of a microprocessor-type peripheral component interface (PCI) block, making the phasemeter design exportable to a variety of computer architectures. The PCI interface can transfer an entire block of phasemeter registers at a rate of 10 kHz.
- A few hardware components were added to enable measurement of the heterodyne-signal period, to count reference clock cycles during an averaging cycle, and to utilize the resulting data in such a way as to make the phasemeter immune to drift of the heterodyne frequency. These additions also eliminate the necessity of incorporating, into the phasemeter software, a different reference-clock-cycle parameter for every different heterodyne frequency that might be used.
This work was done by Frank M. Loya of Caltech for NASA’s Jet Propulsion Laboratory. For more information, download the Technical Support Package (free white paper) at www.techbriefs.com/tsp under the Electronics/Computers category. NPO-45484
This Brief includes a Technical Support Package (TSP).
Modified Phasemeter for a Heterodyne Laser Interferometer
(reference NPO-45484) is currently available for download from the TSP library.
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