Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics.

This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a low-power solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system’s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

The complete 4×4 SW switching fabric chip (with dimensions 6,618×5,658 mm2), incorporating the switching fabric core synthesized in a standard radiation-tolerant by-process 180-nm CMOS (complementary metal oxide semiconductor) library and four proprietary interfaces, has been fully designed in a BiCMOS technology from Jazz Semiconductor and prepared for fabrication. All critical blocks of the switching fabric have been verified through fabrication of several test chips and demonstrated the radiation tolerance up to TID = l MRad. All main blocks of the fabric have been developed as IP (intellectual property) macro-blocks ready to be integrated into other systems in order to minimize the design time, efforts, and risk.

The complete architecture of a 4×4 switching fabric with selectable SW or ML interfaces has been developed based on the Core code supplied by NASA. The architecture of a custom SW/ML routing port has been developed and evaluated. Based on the detailed investigations, the SiGel20 BiCMOS technology has been selected for the implementation of the proposed SF. A complete library of CML (Chemical Markup Language) cells with full anti-TID and anti-SEE protection by architecture (SPBA) has been developed and simulated. The designed SPBA library has been fully characterized to make it suitable for automatic synthesis procedures. Special techniques required for the adaptation of the new differential library to existing single-ended synthesis software tools have been developed and verified.

A complex test chip based on the SPBA library has been fabricated and tested. The measurement results gathered in accordance with the developed test plan demonstrated the efficiency of the selected approach for the implementation of high-duty logic functions and SerDes systems in particular. The provided SF Core has been fully synthesized and simulated in the SPBA library. In an attempt to minimize the power consumption, the SF Core was re-synthesized in the foundry-provided standard CMOS library. This approach, in combination with a CML-based implementation of routing ports, proved to be optimal.

This work was done by Vladimir Katzman of ADSANTEC for Goddard Space Flight Center. GSC-15818-1


NASA Tech Briefs Magazine

This article first appeared in the April, 2011 issue of NASA Tech Briefs Magazine.

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