Terahertz (THz) frequency radiometers, spectrometers, and radars are promising instruments for the remote sensing of planetary atmospheres such as Mars, Venus, Jupiter, and Saturn, and their moons such as Titan, Europa, Ganymede, and others. For these long-term planetary missions, severe constraints are put on the mass and power budget for the payload instruments.
Conventional approaches that package the terahertz receiver components in machined metal waveguide blocks may be too massive for inter-planetary instruments, especially for high transmitter and/or receiver pixel counts. Metal blocks also incur higher losses when they are cascaded in a serial fashion to build up the instrument. Therefore, ultra-compact receiver architectures are needed to reduce loss as well as the mass and size of receivers with high circuit densities.
One approach for fabricating highly integrated and compact submillimeter-wave transmitter/receiver front-ends is to integrate the W-band and higher-frequency power amplifiers, multipliers, and mixer chips into a single micromachined silicon block. This architecture shrinks the heterodyne receiver front-end elements by an order of magnitude in mass and size compared to conventional metal milling techniques.
Several different micromachining techniques exist for fabrication of these THz circuits, and silicon Deep Reactive Ion Etching (DRIE) was chosen because it offers a wider range of design possibilities while achieving better resolution. Silicon dioxide (SiO2) is used as the only mask or as additional mask for deep etches, to protect the silicon when the resist (PR) is etched away. On average, while doing DRIE, the selectivity PR:silicon ratio is 50:1, but for SiO2, a 150:1 selectivity can be achieved, making it a good hard mask candidate. SiO2 is either deposited with plasma-enhanced chemical vapor deposition (PECVD) or is thermally grown before processing the wafer.
The SiO2 mask is made with varying thicknesses over the wafer, chosen according to the depth of the silicon etch being masked. In this way, the series of etch patterns is exposed sequentially by removing increments of the SiO2 mask uniformly over the entire wafer. Crucially, all lithographic steps that define the multiple silicon etch depths are carried out in the SiO2 mask itself prior to the actual etching of silicon. Because the SiO2 only needs to be a few hundred nanometers deep, photoresist never has to be applied to a surface with few-hundred-micron scale trenches in it, thus avoiding the con-comitant coverage problems.
By using a predefined SiO2 hard mask and a cumulative DRIE etching process, parts can be fabricated that exhibit sharp edges and smooth etch bottoms with depths controlled to 2% tolerance, to form complex multi-depth structures. This process has already been used to fabricate numerous THz structures, and recent results validate the use of silicon for THz circuits as a batch-process alternative to conventional metal machining. This technique enables large pixel-count ultra-compact receiver architectures and extends the use of waveguide based components beyond 2 THz.
This work was done by Cecile Jung-Kubiak, Theodore J. Reck, Goutam Chattopadhyay, Jose V. Siles, Robert H. Lin, Imran Mehdi, Choonsup Lee, Ken B. Cooper, and Alejandro Peralta of Caltech for NASA’s Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:
Innovative Technology Assets Management JPL
Mail Stop 321-123
4800 Oak Grove Drive
Pasadena, CA 91109-8099
Refer to NPO-49123.
This Brief includes a Technical Support Package (TSP).
Multi-Step DRIE Process to Fabricate Silicon-Based THz Components
(reference NPO49123) is currently available for download from the TSP library.
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