This is a modification to technology for realizing durable and stable electrical functionality of high-temperature transistors. This modification is believed crucial to experimental implementation of SiC junction field effect transistors that electrically operated continuously at 500 °C for over 10,000 hours in an air ambient with less than 10% change in operational transistor parameters.

As the reliable operating temperature envelope of integrated silicon electronics has been expanded from 125 °C to temperatures above 200 °C, these electronics have found beneficial use in aerospace, automotive, industrial, and energy production systems. Further extension of the reliable operational envelope of semiconductor electronics above 300 °C is also expected to offer additional benefits to these industries, particularly in aerospace combustion engine applications where temperatures can approach 600 °C.

The revised processing is novel (providing stated benefits) in that the self-aligned ion implantation step is carried out immediately following gate etching, prior to mesa pattern definition etching. Self-aligned ion implantation is carried out with the metal etch mask used to define the junction field effect transistor (JFET) p+ gate region still in place. Therefore, the effective thickness of the mask protecting the n-channel beneath the gate region from the ion implantation is thicker (metal mask thickness added to the p+ SiC gate thickness), enabling a higher-energy, higher-dose, and/or simpler ion implantation process to be accomplished without the implant affecting the JFET threshold voltage (i.e., without implant penetration beneath the p+ SiC gate).

Self-aligned ion implantation is carried out at room temperature instead of high temperature. Equipment for carrying out room-temperature ion implantation is readily available in the semiconductor industry, whereas carrying out 600 °C high-temperature ion implantation requires specialized equipment with less availability and higher cost. The self-aligned implant is carried out with single-implant energy and dose, instead of multiple-implant energies and doses.

The self-aligned implant with deeper penetration (from higher implant energy) and more dopant dose into the n-channel regions, not underneath the p+ SiC gate, beneficially enables minimization of vertical electric fields along the surface (particularly of the drain end) of the SiC JFET, and improved immunity of the JFET from charge trapping occurring along the top of the SiC JFET surface, while maximizing the peak operating voltages of the JFET relative to shallower self-aligned implants of comparable dose.

The economic benefits of high-temperature electronics to various systems is likely to be orders of magnitude greater than the total market for actual high-temperature electronics. Similarly, sufficiently improved weight, fuel economy, and maintenance over the multi-decade life of a commercial passenger aircraft would also translate into substantial operating cost savings.

This work was done by Philip G. Neudeck of Glenn Research Center. NASA Glenn Research Center seeks to transfer mission technology to benefit U.S. industry. NASA invites inquiries on licensing or collaborating on this technology for commercial applications. For more information, please contact NASA Glenn Research Center’s technology transfer program at This email address is being protected from spambots. You need JavaScript enabled to view it. or visit us on the Web at . Please reference LEW-18432-2.

NASA Tech Briefs Magazine

This article first appeared in the June, 2015 issue of NASA Tech Briefs Magazine.

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