A technique based on electrical-continuity measurements has been proposed as a means of monitoring and controlling the thicknesses of semiconductor wafers during lapping, polishing, and etching. The technique is expected to contribute to the development of microelectromechanical systems by making it possible to lap and polish wafers with precision greater than has been achieved previously, thereby further making it possible to fabricate wafers of unprecedented thinness (thicknesses of 5 µm or possibly even less). Unlike some prior techniques for measuring the thicknesses of semiconductor wafers, this technique does not entail the timeconsuming intermittent stopping of processing to take measurements. Also, in comparison with most prior techniques, this technique offers the potential for greater precision at lower cost.
The technique involves preparing a wafer by forming one or more thin electrical conductor(s) within it at a depth that corresponds to the desired final thickness. During processing of the wafer, one would monitor the electrical resistance(s) of the conductor(s) to detect an increase in resistance as an indication that conductor material had been removed and thus the removal of material from the wafer had brought the wafer to the desired thickness. The increase in electrical resistance could serve as a control signal to stop the removal (lapping, polishing, or etching) process.
The figure depicts salient aspects of the technique in more detail at several stages of processing. There would be two wafers: the target wafer (the one to be thinned to a specified thickness) and a carrier wafer. By use of photolithography, one or more hole(s) of depth equal to the desired final thickness would be etched into the target wafer from its back side. Thin strips of metal (to serve as the electrical conductors) would be deposited and patterned on the back side; the strips would extend continuously from one edge of the wafer to the opposite edge and would extend all the way into the hole(s).
The thickness-controlling etched holes (dimples) are located in dead spaces on the target substrate. Such dead spaces are the grids that define the edge of individual chip cells. Therefore, the dimples do not reside within active areas of the chip or substrate.
The carrier wafer would either be made of, or coated with, an electrically insulating material, and would have a diameter slightly less than that of the target wafer. The back side of the target wafer would be bonded to a face of the carrier wafer so that the carrier wafer could serve as a platform to hold the target wafer during processing to thin the target wafer. Because of the smaller diameter of the carrier wafer, the ends of the electrical conductor(s) on the target wafer would protrude slightly past the edge of the carrier wafer and would thus be accessible for measurement of electrical resistance. During processing, target-wafer material would be removed from the front side of the target wafer. Processing would be continued until the aforementioned increase in electrical resistance occurred.
This technique offers two fabrication options. It may be possible to selectively dissolve the carrier substrate and the conducting strips, thereby releasing the thin target wafer for further processing. Also, the carrier wafer and the conducting strips can become functional components of the final device.
This work was done by Robert S. Okojie of Glenn Research Center. For further information, access the Technical Support Package (TSP) free on-line at www.nasatech.com/tsp under the Manufacturing category.
Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Commercial Technology Office, Attn: Steve Fedor, Mail Stop 4–8, 21000 Brookpark Road, Cleveland, Ohio 44135. Refer to LEW-17022.