A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors.
Faults Are Detected in this prototype system by comparison of the outputs of the two processors, which are embedded in a single FPGA. The legend “FI” denotes locations where faults are inserted for testing purpose.
A working prototype (see figure) consists of two embedded IBM PowerPC®405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.
This work was done by Gary Bolotin, Robert Watson, Sunant Katanyoutanant, Gary Burke, and Mandy Wang of Caltech for NASA’s Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Semiconductors & ICs category. NPO-40575
This Brief includes a Technical Support Package (TSP).
Multiple Embedded Processors for Fault-Tolerant Computing
(reference NPO-40575) is currently available for download from the TSP library.
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