A regio-regular poly (3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.

Figure 1. This cross-sectional view of the Basic FET shows (a) the global gate FET and (b) split-gate FET.
Figure 1(a) shows a schematic cross-sectional view of the basic FET using an insulating gate dielectric layer over a doped silicon substrate. Two metal leads patterned over the insulator serve as the source and drain terminals of the device while the doped silicon serves as the global gate electrode. In this basic configuration, the gate voltage is applied to the bottom side of the wafer. To complete the FET, an organic semiconducting channel is placed between the source and drain terminals either via electrochemical deposition, vacuum deposition, or spin coating of the semiconductor material, resulting in a two-dimensional thin-film morphology; or via electrospinning, resulting in a one-dimensional nanofibrous morphology. In the dual-input architecture shown in Figure 1(b), metal contacts are located beneath the gate dielectric, and are accessed from the top side of the wafer by vias etched into the gate dielectric and semiconducting layers. Each gate contact serves as a device input, thus allowing for the design of various types of logic gates.

The dual-input device demonstrates AND logic functionality (see Figure 2), and is controlled by applying either 0 or –10 volts to each of the gate electrodes. When –10 volts are simultaneously applied to both gates, the transistor is conductive (ON), while any other combination of gate voltages renders the transistor highly resistive (OFF). The p-type carrier charge mobility is about 5 × 10–4cm2/V-s. The low mobility is attributed to the sharp contours of the RRP3HT film between the drain and the source contacts, and to defects in the RRP3HT film itself.

The device substrates are fabricated with a starting wafer that is n-type doped Si (10 ohm-cm), with a 200-nm thick, thermally grown oxide layer. First, the gate metals, comprising 20-nm Cr/100-nm Au, are vacuum deposited in a thermal evaporator and patterned using conventional photolithographic and liftoff techniques. Next, a 100-nm-thick silicon nitride (Si3N4) film is deposited over this using chemical vapor deposition (CVD). Access to the gate metallization is obtained by etching windows into the silicon nitride. The source and drain metallization, comprising 20-nm Cr/100-nm Au, is deposited on the CVD-grown silicon nitride on either side of the buried split gates using conventional photolithographic and liftoff techniques. The electrode "fingers" are about 20 microns wide and 600 microns long. The spacing between the electrodes is approximately 4 microns.

The split-gate architecture for logic circuitry is demonstrated via a two-input logic AND circuit. To create the device, a 10-Megohm load resistor is connected between the ground and the transistor source terminals, with the two gate terminals serving as the inputs. The output (VR) is taken at the source terminal across the load resistor. A low frequency ( 0.01 Hz) square-wave signal serves as the input gate bias. For all combinations of VGS1 and VGS2, except VGS1 = VGS2 = –10 V, the transistor is in the resistive "OFF" state, and –0.3 mV < VR < 0 V. For VGS1= VGS2 – 10 V, the transistor is in the more conductive "ON" state, causing a greater portion of the voltage drop to occur across the load resistor. As a result, VR is a more negative value (–1.8 mV< VR < –1.7 mV).

Figure 2. Drain-Source Current vs Drain–Source Voltage Characteristics are shown for the split gate field-effect transistor at different gate-source voltages.
When the device functions as an AND logic circuit, VGS1 and VGS2 are functions of time, while corresponding change in the output of voltage VR is a function of time for the four possible combinations of VGS1 and VGS2 = 0 or –10 V. Larger outputs are observed only when both gates are simultaneously biased "high."

This work was done by N. Theofylaktos and F.A. Miranda of Glenn Research Center; N.J. Pinto and R. Perez of the University of Puerto Rico-Humacao; and C.H. Mueller of Analex Corporation.

Inquiries concerning rights for the commercial use of this invention should be addressed to NASA Glenn Research Center, Innovative Partnerships Office, Attn: Steve Fedor, Mail Stop 4–8, 21000 Brookpark Road, Cleveland, Ohio 44135. Refer to LEW-18214-1.

NASA Tech Briefs Magazine

This article first appeared in the April, 2008 issue of NASA Tech Briefs Magazine.

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