CACHESIM is a C-language computer program that simulates (1) cache-memory options associated with a computer hardware design concept and (2) related properties that can be expected to affect the overall performance of the computer, before the computer is constructed. Heretofore, the performance effects of cache-memory options were investigated through hardware monitoring. CACHESIM provides for selection of options that include hardware organization, cache size, line size, replacement policy, write-hit policy, write-miss policy, fetch policy, simulated processor speed, processor instruction-execution clock cycles, and cache-miss clock-cycle penalty. For a given combination of options, the output of CACHESIM includes appropriate hit and miss rates, central-processing-unit time, and the number of memory stall cycles incurred. This information is useful in determining the overall effectiveness and performance of the cache design.

This work was done by José J. Amador of Kennedy Space Center.For further information, access the Technical Support Package (TSP) free on-line at under the Computer Software category, or circle no. 172 on the TSP Order Card in this issue to receive a copy by mail ($5 charge).


NASA Tech Briefs Magazine

This article first appeared in the March, 1998 issue of NASA Tech Briefs Magazine.

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