Engineers have devised a simple, reproducible, and less expensive approach to manufacturing computer chips using directed self-assembly, which can increase the density of circuit patterns. The method could mean a boost in functionality for semiconductor electronics, and in capacity for data storage.
Computer chip makers continuously strive to pack more transistors in less space, yet as the size of those transistors approaches the atomic scale, there are physical limits on how small they are able to make the patterns for the circuitry. Taking advantage of a germanium wafer coated with a layer of virtually pristine graphene, engineers devised a simpler, reproducible, and less expensive manufacturing approach using directed self-assembly.
Directed self-assembly is a large-scale, nano-patterning technique that can increase the density of circuit patterns and circumvent some limitations of conventional lithographic processes for printing circuits on wafers of semiconductors such as silicon. The method enables the fabrication of intricate, perfectly ordered polymer patterns for circuitry.