PCI Express is the peripheral bus now being adopted by next-generation PCs, servers, and industrial computers. It provides a scaleable, high-bandwidth, point-to-point pathway between peripheral cards and the computing core while retaining application software compatibility with previous generations. For machine-vision systems, the architecture and higher bandwidth of PCI Express yield major increases in achievable frame rate and image size as well as simplifying the implementation of multi-channel capability.

Figure 1: Rather than sharing a set of connections among many peripheral cards as in the traditional PCI bus, PCI Express uses switched serial links to provide a direct, full-bandwidth connection between any two nodes on the bus.
The PCI Special Interest Group (PCISIG) created PCI Express as a solution to the increasing mismatch between the PC's peripheral card bus and the I/O demands of high-performance graphics, communications, and storage. The traditional PCI bus had run into hard limits to its clock speed caused by skew across the parallel bus. The highest performance PCI bus achievable runs at 66 MHz with a 64-bit data pathway, for a data rate of 528 Mbytes/second.

The PCISIG developed an intermediate solution called PCI-X that aimed to provide higher bandwidth while still utilizing a parallel bus structure by running as fast as 266 MHz. The design of PCI-X peripherals was both complex and costly, however, and developers typically limited their systems to 133 MHz for a data rate of 1 Gbyte/second. Even at this lower speed, skew and loading considerations limited the fan-out to only a few peripheral cards. Since PCI-X did not prove satisfactory, an entirely different solution was needed.

PCI Express (PCIe) eliminates the skew and fan-out limitations of high-speed parallel buses by adopting a serial bus structure. A PCIe connection is made point-to-point through a switch matrix, providing a direct link between the two communicating entities (see Figure 1). This direct link ensures that a data transfer is able to utilize the full bus bandwidth; there is no sharing of the bus with other connections during the transfer.

The physical arrangement of a PCIe link is through a set of serial lanes, with groupings of 1, 2, 4, 8, 12, 16, or 32 lanes allowed. Each lane operates at 2.5 Gbits/second using 8b/10b coding to provide a self-clocking 250 Mbyte/second data rate in each direction. Thus, a four-lane link provides 1 Gbyte/second and a 16-lane link provides 4 Gbytes/second per direction, significantly higher than the PCI bus can achieve. Further, the PCIe bus has considerable expansion potential. The recently-introduced PCIe 2.0 specification allows the links to run at 5.0 Gbits/second for double the data rate, and higher link rates are in development.