Software Compatibility Retained

Even though PCIe uses a serial connection at the physical layer, however, it retains backward compatibility with PCI peripherals at the driver, operating system, and application levels. The hardware for a PCIe link handles the transition from parallel, memory-mapped data transfers of PCI to the switched serial transactions of PCIe. Even the interrupt and other out-of-band signals of PCI map into the serial PCIe, so that the software is unaware of the bus change.

Figure 2: By supporting 64-bit addressing, PCIe can bypass the memory addressing limitations of older 32-bit PCI systems, providing direct access to a virtually unlimited address space with no need for virtual memory.
PCIe hardware handles this translation in three stages. At the physical layer, hardware automatically converts parallel data transfers into serial blocks and stripes the data across available lanes to fully utilize the link bandwidth. Each serial block contains addressing and identification bits that allow the physical layer hardware at the receiving end to deserialize and reassemble the data in the correct order, eliminating any skew present between lanes. The physical layer also handles lane width negotiations during system initialization, matching its output to the channel available.

Link-layer hardware provides error detection and correction for data transfers, operating at the block level. If a data transfer error occurs, the link-layer hardware automatically resends the block without the intervention of the upper layers. From the standpoint of the transaction and higher layers, an error event simply looks like a longer than usual response time for acknowledging the transaction.

The transaction layer of PCIe provides all of the conversion between memory-mapped PCI data transfer, command, and out-of-band signaling and the address-driven serial PCIe signals. The command and data interfaces between the transaction layer and the rest of the computer system are identical to those used by the PCI transaction layer. Thus, the hardware drivers, operating system, and applications software of a computer system remain unaltered when interacting with a PCIe peripheral.

Advantages of PCIe

This move to PCI Express provides PC-based system developers with a number of advantages. One is an increased ability to balance cost and performance. Designers only need to use as many lanes in their design as their performance requirements dictate. Given that the bus width is only four wires per lane, connector costs drop as well.

Another advantage of PCIe is that the bus's dedicated connection helps eliminate system bottlenecks. The bandwidth of the PCI bus had to be shared among all the peripherals and other system functions, so that the available bandwidth decreased with each additional peripheral. PCIe is a switched point-to-point connection and allows peer-to-peer communications. This means that a data transfer has a dedicated link available to it and does not need to share bandwidth during the transfer. In addition, the peer-to-peer capability allows multiple transactions to occur simultaneously if a non-blocking switch is used. Further, peripheral devices can stream data direct to system memory without CPU intervention while the CPU is performing other tasks.