With each new generation of FPGA devices, Xilinx continues to push the performance envelope to match the ever-increasing requirements of target applications. The recent announcement of the Virtex-6 is no exception. More processing power, lower power consumption and updated interface features to match the latest technology I/O requirements are all part of the new devices. While it might be easy to assume that faster, bigger, more powerful is better, it’s important to understand how the latest FPGA innovations actually deliver this higher performance to best match the device to the specific requirements of the application.
Logic Cells, Slices and Blocks
Virtex FPGAs follow a naming convention that includes the size of the device in the name. Specifically, the approximate number of logic cells contained in the part is included in the part number. For example a Virtex-6 LX240T device contains approximately 240,000 logic cells, while a Virtex-5 SX95T contains approximately 95,000 logic cells. Sounds simple, and it is, but just comparing the amount of logic cells can be misleading.
Logic cells consist of combinational logic that creates a lookup table, which implements functions such as AND, OR, NAND, and addition. Flip flops and the connections to the adjacent cells are also implemented in the logic cell. Multiple logic cells are grouped together to create a single unit, called a slice.
As the architecture of the Virtex has evolved, the number of logic cells in a slice has changed: a Virtex-4 slice consists of approximately two logic cells, Virtex-5 and Virtex-6 slices consist of approximately six logic cells.
The next step up on the architectural hierarchy is the CLB (Configurable Logic Block). Here again, the development of more powerful CLBs has changed the relationship between slices and CLBs: a Virtex-4 CLB consists of four slices and Virtex-5 and Virtex-6 CLBs consist of two slices. As a result, Virtex-4 CLBs require eight logic cells and Virtex-5 or Virtex-6 require 12 logic cells. Figure 1 compares these parameters in the three Xilinx generations.
So why did Xilinx design FPGA logic in this hierarchical organization instead of just creating a flat plane of interconnected logic cells? The multilevel design of modern FPGA devices creates a balance between interconnect speed and interconnect flexibility.
The fastest connections exist between logic cells. Connections between slices are slower and connections between CLBs are even slower. Going in the other direction, connections between CLBs are the most flexible and general purpose, slice connections are a bit less flexible, and connections between logic cells are more limited.
With each new generation of FPGAs comes higher component density in the form of more logic cells. Figure 2 graphs the logic cell densities of various devices from the last three Virtex generations. For each generation, Xilinx offers a range of different density devices within a single package type. To focus the scope of this comparison, all of the devices compared are available in the same 35mm x 35mm BGA (Ball-Grid Array) package.