Since Virtex-4 CLBs comprise eight logic cells, while Virtex-5 and Virtex-6 CLBs comprise 12, the increase in logic cells between Virtex-4 and Virtex-5 actually translates to a decrease in CLBs because each CLB in the Virtex-5 requires more logic cells. While the Virtex-5 CLBs are more powerful than their Virtex-4 counterparts, there are still fewer of them to use so the overall performance increase is somewhat reduced. What is clear from this graph is that the Virtex-6 represents a significant increase in density from the Virtex-5 family.
Geometries, Speed and Power
So how are more logic cells packed into the same size package with each new generation? As you might expect, by shrinking the physical size of the logic. IC geometries are measured in nm (nanometers). The progression from Virtex-4 through Virtex-6 has been from 90nm to 65nm to 40nm. An additional benefit of shrinking transistors is an increase in switching rates, which translates to faster clock speeds. Virtex4 runs at 500 MHz, Virtex-5 runs at 550 MHz and Virtex-6 achieves a 600 MHz clock rate.
Unfortunately, whether it’s lunch or shrinking transistors, nothing comes for free. Leakage current tends to increase exponentially as the transistors shrink, increasing the static power, even when the transistors aren’t switching. To compensate, Xilinx has introduced a series of power saving design techniques. Depending on the mode the FPGA is operating in, a power savings of between 20% and 40% can be achieved on the Virtex-6 when compared to comparable Virtex-4 devices. Again, as densities increase and more logic cells are packed in the same size device, these power savings become imperative.
DSPs and Memory
In addition to CLBs, Virtex FPGAs contain DSP slices. These are dedicated multipliers, multiply-accumulator, or multiply-adder blocks. The DSP slices are responsible for the majority of the processing horsepower of FPGAs. Like the CLBs, the DSPs benefit from a compound performance increase with each new generation: improvements in the actual DSP architecture; increases in operational speed from 500 MHz to 550 MHz to 600 MHz with the latest generation; and increasing density allowing more DSP slices to be included in the same size package. While the largest Virtex-4 device includes 512 DSP slices, the Virtex-6 tops out at an impressive 2016.
New to the improved Virtex-6 DSP slice (DSP48E1) is a 25-bit pre-adder positioned before the more traditional multiply-accumulator (MAC) stage. The pre-adder is ideal for implementing functions like filters, which are ubiquitous in radar and communications systems. Previous FPGA families required building the filters in CLBs, which operated slower and consumed logic that might be best used for other functions.
All Virtex FPGAs include integrated memory blocks (Block RAM) for implementing anything from random access storage to dual-port architectures, to FIFOs depending on the application. For the 35mm x 35mm package we’ve been comparing, Block RAM has increased from a maximum of approximately 7 megabits to 8 megabits between the Virtex-4 and Virtex-5; it then took a sizable leap to a maximum of 38 megabits for the Virtex-6.
Connecting It All Together
Through the last few generations of Virtex devices, BGA ball pitch has remained the same at 1mm, which means there is 1mm spacing between the BGA balls. In a 35mm x 35mm device, this turns out to be a grid of between 1136 and 1156 balls, depending on the device. Because of this, I/O density hasn’t really seen an increase, but the number of different I/O signal types has been expanded as well as I/O speed. The general purpose I/O, SelectIO, is used for connecting everything from devices like A/Ds and D/As, creating parallel and serial data buses, or implementing memory interfaces. The Virtex-6 family is compatible with the latest QDRII+ and DDR3 technology and Xilinx provides examples for implementing interfaces to these devices.