With multiple switched interconnects gaining momentum in the embedded space, selecting just one to address a wide range of military systems requirements is not easy.
Individually, switched fabrics such as Gigabit Ethernet (GbE), Serial RapidIO (SRIO), and PCI Express (PCIe) have their own particular technical merits, and each is poised to carve out a piece of the interconnect market. However, when combined in next-generation Serial Switched Backplanes (SSB) like VPX (VITA 46/48), multi-fabric switching can enable powerful new military architectures by leveraging 'best of breed' interconnect technology to address specific application requirements ( Figure 1).
For example, loosely coupled systemwide network connectivity ideally can be architected with low-cost switched 1/10 GbE. A switched GbE Intra-Platform Network (IPN) can be used to efficiently transport IPv4/v6 packets between different boxes using standardized cabling, or between blades and processors through standardized backplanes.
Meanwhile, for high-performance data movement or real-time deterministic messaging, either SRIO or PCIe, or a combination of both, can be used to create tightly coupled communication clusters among processors, peripherals, and blades. SRIO is a natural fit for meshed digital signal processing applications, while PCIe can be used for core processor-to-peripheral high-bandwidth data movement.
Switched GbE — The Ideal IP Transport
Switched Gigabit Ethernet is being driven into military platforms through top-down networking initiatives such as the Global Information Grid (GIG), Network Centric Operations (NCO), and the adoption of IPv6 as the common communications protocol.
The result is a convergence toward 1/10 GbE as the fabric of choice for IP-based vehicular networks. Legacy systems are being transformed by adding GbE switch blades to form star or redundant dual-star networks within a VME64x box. New systems can leverage VPX backplanes to allow not just 1 GbE, but also 10 GbE interfaces in the backplane.
Although there are many existing standards for GbE, some of the more popular ones along with their key features include:
- 1000 BaseT is typically used with copper backplanes for blade-to-blade or CPU-to-CPU communications; 1000 BaseSX is used for box-to-box optic connections; and XAUI for 10-GbE stacking or backbones.
- Each 1-GbE interface can auto-negotiate between 10 Mbps, 100 Mbps, and 1000 Mbps, or through link aggregation, can achieve multi-Gbps rates.
- Near-future standards for Ethernet show promise to evolve to 802.3ap in the backplane (1000 BaseKX over 1 lane, 10 GBaseKX4 over 4 lanes, and 10 GBaseKR over 1 lane).
- Next-generation 1/10 GbE switch chips are arriving on the market where each port can operate at 1, 2.5, 5, and 10 Gbps line rates.
- Optimized 1 and 10 GbE NIC chips are arriving on the market that can remove networking bottlenecks through Remote Direct Memory Access (RDMA) and protocol offload (e.g., a 10 GbE iWARP NIC can achieve 800 MBps with minimal loading on the processor for large data transfers).
Already commoditized in the commercial world with an ever-increasing ecosystem that continuously drives down component costs while increasing performance, switch Gigabit Ethernet is now rapidly finding its way into just about every major military platform.
Serial RapidIO (SRIO) is poised to play the role of the "inside the box" high-performance data mover in multi-processor signal-processing applications. SRIO's strength lies in its combination of low overhead and high-speed characteristics with features that make it one of the most suitable fabrics for processor-to-processor communications.
Radar, EW, ELINT, and other sensor systems are constructed with multiprocessor implementations, involving the flow of large datasets internally. Frequently, it is the performance of inter-processor data transfers, rather than the raw computing power, that limits the overall performance of the system. The introduction of the VPX module format, in conjunction with the rollout of processors and FPGAs with SRIO interfaces, means that developers will be able to easily construct COTS-based systems with dramatically higher internal bandwidth. A SRIO implementation will provide 10 GBps of bandwidth to the backplane, versus today's best VME/StarFabric implementations that top out around 1 GBps.
SRIO is a point-to-point switched serial technology featuring:
- 1.25, 2.5, or 3.125 Gbps signaling rate
- A SRIO port with 1 or 4 lanes for a maximum data rate of 1.25 GBps per port in each direction
- 8 B/10 B encoding and end-to-end packet CRC
- Four levels of priority
- Support for multi-cast
- Support for global memory
- Support for redundant routes for high-availability applications
- Messaging and doorbell features for efficient inter-processor exchanges
Curtiss-Wright's CHAMP-AV6 Quad PowerPC 8641 DSP board is an example of the next generation of modules taking advantage of the high-speed connectors for the VPX format to harness the bandwidth advantages of the SRIO fabric.
PCIe in Mil/Aero
The mainstream PCI Express (PCIe) interface—the same fabric as commonly used in current desktop, laptop, and server PCs—is now finding its way into advanced single-board computer and digital signal processing modules targeted for deployed mil/aero applications. The widespread use of PCIe in volume PC applications drives down the cost of PCIe switches and PCIe peripherals, making cost effectiveness one of its major benefits. Despite approaching commodity status in the PC world, PCIe incorporates a number of sophisticated technical features that together make it one of the most advanced fabrics currently available.
Some of the key features of PCIe include:
- Communications are point-to-point. Each link (point-to-point connection) can consist of 1, 2, 4, 8, 16, or 32 lanes.
- Each lane consists of one transmit (Tx) and one receive (Rx) pair signaling at 2.5 Gbaud, yielding a nominal data rate of 250 MBps in each direction per lane, or an aggregate data rate of 4 GBps for a typical 8-lane link.
- 8 B/10 B encoding of each data byte and end-to-end CRC on each packet provides robust error detection.
- A packet acknowledgement protocol with automatic retransmission on errors provides end-to-end reliable data transmission with no software overhead.
- Prioritization of data flows ("quality of service").
- Physical layer incorporates bit scrambling to reduce EMI (by eliminating long sequences of 1s or 0s that create a square wave).
- The electrical signaling layer incorporates pre-emphasis/deemphasis to optimize signal integrity, allowing lower cost materials to be used for printed circuit boards and connectors.
The advanced technical features of PCI Express, its wide adoption in the general IT industry, and its software compatibility with the ubiquitous conventional PCI standard make it a natural choice for incorporation in high-performance embedded mil/aero computing systems.
As illustrated by the discussion above, new serial switched fabric technologies are enabling mil/aero embedded computing systems to achieve new levels of functional density while reducing system cost and weight (see Figure 2). Of the panoply of existing and emerging fabric technologies, three stand out as offering particular benefit—GbE as the standard bearer of IP-based data traffic whether on intra-platform networks or within a standard backplane-based subsystem; SRIO for interconnecting dense multi-computing clusters for DSP applications; and PCIe for core processor-to-peripheral high-band-width data flows.