Both Serial RapidIO and Ethernet are being used as a backplane interconnect technology in a wide range of embedded applications. Many suppliers support both standards and let designers choose to work with whichever interconnect they feel is best. This neutral position provides interesting insights into both of these technologies. From a high-level point of view, it seems as if these two technologies are in stiff competition with each other. While Ethernet is certainly the incumbent technology, Serial RapidIO has had a huge uptake in adoption over the past year, with more silicon vendors supporting the standard than was originally anticipated.

Even for those applications where native Serial RapidIO processor interfaces seem to be limited, efficient bridging silicon to those interfaces that are supported is readily available. While it appears that this might be a neck-and-neck race between the two technologies, the reality is that nothing is more sacred in design than adopting the appropriate technology for an application. In other words, the number of design wins isn’t so much a factor of deciding which interconnect to use as a system-level fabric as it is deciding which performs the best for the job at hand.

No Contest

From this perspective, Ethernet and RapidIO aren’t really in competition with each other, despite how they may seem to be pitted against each other by different vendors in the marketplace. In reality, the two standards don’t really compete with each other. Ethernet was designed to connect computers and it just isn’t an appropriate standard to transfer data chip-to-chip. While the argument of Ethernet’s high volumes and economies of scale applies to LAN and WAN applications, the features and higher layer protocols required for system-level fabrics comprise a completely different ecosystem with considerably lower volumes and higher costs. Additionally, Ethernet’s switching capabilities are overkill for point-to-point links and needlessly increase system complexity, latency, and cost in these applications.

Serial RapidIO, in contrast, was designed as a pure chip-to-chip interconnect, which is the foundation of backplane, chassis-to-chassis, and other system fabric applications. Since it has the protocol layer built-in and implemented in hardware, it is an efficient and simple interconnect protocol to use. Serial RapidIO is already widely accepted in many high-performance embedded systems that utilize anywhere from one to hundreds of DSPs and FPGAs spread across multiple boards, including military (radar, etc.), wireless, and industrial control applications. In fact, for WiMAX modem cards and base station applications, Serial RapidIO is the undisputed leader.

Ethernet in the Backplane

Backplane applications are effectively chip-to-chip transfers, just over longer traces and across connectors (see Figure 1). Currently, the inefficiencies of Ethernet make it suboptimal for these applications, particularly in terms of reliability, effective throughput, responsiveness, and overall latency. Reliability is the Achilles’ heel of Ethernet. In order to reduce system cost, many developers use a single fabric to transport both application data and control plane traffic. Ethernet’s best-effort service, however, is insufficient to transport control plane traffic in a reliable fashion. For this reason, TCP/IP is required to compensate for dropped packets, leading to additional latency and implementation complexity. Serial RapidIO, on the other hand, guarantees packet delivery as part of the base specification and therefore is robust enough as a system fabric to carry control plane traffic reliably. As applications become more complex and process more data more quickly, effective throughput has become a major bottleneck for Ethernet-based systems.

Many applications have used 10/100 Ethernet over the backplane with success, but only when over-provisioning of at least 4X has been implemented to reduce the frequency of dropped packets. As these applications increase in performance, however, Ethernet quickly hits its capacity limits. Serial RapidIO only requires over-provisioning on the order of 20 to 25% in order to cover the bit errors that are an unavoidable part of high-speed serial communications. The difference in actual throughput is staggering. Consider an industrial application transferring data on the order of 10 Gbps. With over-provisioning, Ethernet maxes out at a theoretical best throughput of 2.5 Gbps, while Serial RapidIO exceeds 7.5 Gbps. Further increasing effective throughput is Serial RapidIO’s lower overhead (14-20 bytes compared to Ethernet’s 38 bytes) and higher efficiency at the smaller payload sizes common to backplane applications (see Table). Serial RapidIO also has the great strength of providing link-level flow control. This means that errors are handled in hardware at the MAC/link layer, minimizing latency and improving system responsiveness to errors. Ethernet, on the other hand, handles errors at layers 3 and 4, which means they are taken care of in a software protocol stack. As a result, error recovery introduces high overhead and latency, two factors that developers struggle to minimize over high-speed backplanes.

Chassis-to-chassis (top) and other system fabric applications.

Leveraging Ethernet’s Maturity

One potential point of confusion is the fact that the Serial RapidIO electrical layer is effectively a XAUI interface. Many developers associate XAUI with Ethernet and mistakenly assume that all XAUI backplanes are Ethernet based. Serial RapidIO was intentionally designed to match the XAUI specification so that developers using Serial RapidIO could leverage the existing XAUI ecosystem that Ethernet has already developed. This is another key strength of Serial RapidIO as its 3 data rates all follow standard specifications: 1.25 Gbps follows 1000 Base-X, 2.5 Gbps follows PCI-Express, and 3.125 Gbps follows XAUI. By basing the electrical layer on these three very mature eco-systems, Serial RapidIO has been able to take advantage of interface economies of scale from its inception.

While Ethernet’s larger payload offers better efficiency with maximum payloads, Serial RapidIO’s lower overhead and smaller payload make it more efficient with the payload sizes common to back- plane applications. Note that these base figures do not take into account over provisioning.

Serial RapidIO was designed from the start to minimize overhead and latency for chip-to-chip data transfers. Certainly, one can force any interconnect into any application, but the results will be less than optimal, and this is a fact that developers who select Ethernet for backplane, inter-chassis, and other system-level fabric applications because they are familiar with it quickly discover. Currently there is an Ethernet backplane standard under development which is attempting to address the inefficiencies of Ethernet for chip-to-chip interconnections, but it is not yet available. However, even if its inefficiencies have been sufficiently addressed once it is finalized, it will lack the extensive ecosystem and widespread industry support that Serial RapidIO already enjoys today.

This article was written by Ramanand Venkata, Product Marketing Manager, Altera Corporation (San Jose, CA). For more information, contact This email address is being protected from spambots. You need JavaScript enabled to view it. or visit .