The trick to exploiting the ultra lowpower characteristics of microcontrollers with 100 nA sleep mode power consumption is to keep them in sleep mode as much as possible. The problem is that the growing number of on-chip peripherals and the increasingly dataand interrupt-intensive nature of modern applications make this a very difficult objective to achieve.

As embedded applications become more responsive to their environments, the number of peripherals that capture and process environmental data is increasing rapidly. It is commonplace for microcontrollers to have ADCs, DACs, PWMs, multiple timer/counters and numerous I2C, SPI, CAN, USB and USART interfaces for communications. In addition, the number of interrupts and amount of data that must be moved between the memories and the peripherals has grown exponentially, increasing the CPU load and consuming more power. The context switching and interrupt usage for two simultaneous interperipheral communications and a single 64 Mbps data transfer requires 200 CPU MIPS and consumes 100 mA.

Peripheral signals often do not require the CPU to do anything except let another peripheral know it needs to do something. Unfortunately, liaising between two peripherals requires cycle intensive interrupt processing. For example, in a motor control application, overheating is prevented by constantly measuring the current on the motor and toggling an analog comparator when an overcurrent situation signals that the motor has stalled. The CPU is interrupted and shuts down the pulse width modulator (PWM) output for the motor driver. This process can require tens of cycles, and another 20-100 cycles to restore the context. The microcontroller is not really doing anything that requires its processing capabilities; it is basically just passing a message from an analog comparator to a PWM output. The cycles are basically wasted.

Other cycle wasters include the use of timer/counters to time other peripherals such as ADCs and DACs. In these situations, an interrupt is generated to start every conversion. At a sample rate of just a few kHz, these timer/counter interrupts consume over 1 MIPS — about 8% of a 12 MIPS MCU’s capacity.

One solution to this problem is to use a microcontroller with an event system and DMA that off-load these functions from the CPU. Ultra-low-power, single-cycle RISC 8/16-bit MCUs are available with multi-channel event systems and DMA controllers that allow the simultaneous execution of up to 8 inter-peripheral events, plus up to four 64 Mbps data transfers, while consuming less than 10 mA. Since the event system and DMA allow the peripherals to communicate with each other autonomously, no CPU clock cycles or interrupts are required. The CPU can be put into idle sleep mode.

The event system routes peripherals signals through a dedicated network outside the CPU data bus and DMA controller. The benefit of this is predictable and latency-free inter-peripheral signal communication that reduces CPU time and frees up interrupt resources. The event system enables a change of state in one peripheral to automatically trigger actions in other peripherals. In the motor control example cited earlier, an analog comparator, timer/counter, I/O pin or ADC in the microcontroller can directly shut off the PWM for the motor drive within two cycles of an over-current situation, offering better protection for the motor, while using zero interrupts and zero CPU cycles (Figure 1).

Figure 1: XMEGA with Event System Bus

Peripheral events that can trigger the event system include timer/counter compare match or overflow, analog comparator toggle, pin change, ADC complete or compare function, and real time counter overflow. Events that can be triggered in other peripherals include ADC or DAC conversion start, input capture to time stamp communication or ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction, or changing a pin output.

Deciding which events should trigger which actions on which peripherals is fully configurable and completely up to the designer. Event system configurations can be kept static and locked, or can change dynamically during various stages of the application execution. The event channels operate in parallel and up to 8 pairs of peripherals can be interconnected simultaneously at any time.

Figure 2: Event Handler

Using an event system removes the bottlenecks associated with multiple and/or frequently triggering interrupts. There is no software overhead and critical tasks can be performed independently of the CPU. The implications for power consumption are significant. A conventional 8-bit MCU, without an event system, requires about 16 MIPS to shut off a PWM in response to an overcurrent condition on a motor measured by a fast ADC. At 16 MHz, 1 MIPS/MHz, and 0.5 mA/MHz, the microcontroller would consume 8 mA for this task alone. A comparable MCU with an event system would require zero MIPS, and no incremental power consumption (Figure 2).

Table 1. Event Processing Cycles and Response Times.

An extra bonus is that by eliminating the interrupt, processing response latency can be reduced to a guaranteed maximum of two clock cycles — or 62.5 nS with a 32 MHz clock. The fastest possible response time is 31.2 nS. In fact, using an event system on an 8-/16-bit MCU can achieve event response times that are 37 times faster than that available from a conventional 32-bit MCU without an event system (Table 1).

Transferring data is another cycle-intensive contributor to power consumption. Since a CPU can transfer only one-byte of data at a time, there is a lot of processing overhead involved. An 8- bit microcontroller must execute 22 MIPS and consume 11 mA to effect a 350 KBps data transfer. SPI and USART transfers can have data rates higher than several Mbps, making it virtually impossible for a traditional 8/16-bit MCU to support these rates.

Adding a peripheral DMA controller off-loads essentially all these cycles from the CPU. When the CPU data bus is free, the DMA controller uses it to transfer data between the memories and peripherals without using CPU resources. In some devices, the internal buses to the peripheral registers including IO pins, memory mapped EEPROM, internal SRAM, and the External Bus Interface are split to enable simultaneous bus access from the DMA controller and the CPU. Hence there is always a communication channel available for the DMA (Table 2).

Table 2. MIPS and MCU Power Consumption.

Transferring 350 KBps of data with a DMA controller requires 99% fewer MIPS and consumes less than 1 mA, compared with 22 MIPS and 11 mA for an 8-bit MCU without DMA.

The DMA controller can move data from a peripheral register to internal or external SRAM, between SRAM locations, and even between peripheral registers directly. The four DMA channels have individual priority, source, destination, triggers, addressing modes, and transfer block sizes. The DMA can transmit from 1 Byte to 16M Bytes in a single transaction, due to the simple linear data memory address space in the RISC CPU and auto increment/ decrement and reload features in the DMA controller.

Figure 3: Event Processing

Using the event system in conjunction with the DMA controller, an analog-to-digital and digital-to analog conversion can be achieved as follows: A pin-change on any I/O pin or an overflow on any timer/counter triggers the ADC conversion without any CPU cycles. The ADC conversion result is transferred over a DMA channel to the SRAM. At the same time, a second timer/counter can trigger a high speed DAC conversion, using a second DMA channel for the data. The event system can make the analog comparator trigger input capture for 100% accurate time stamps, automatic capture to time stamp the beginning of communication transactions, or ADC conversion scans on the second ADC. Four event channels are still available that can be used for fault protection of a PWM output controlling a high voltage driver stage, cascading of timer/counters, and a couple of communication channels all at the same time, all while the CPU is sleeping (Figure 3).

Table 3. Comparative interrupts, MIPS, and Power Consumption for 350 Khps data transfer.

Adding an event system and DMA to a microcontroller can have an enormous impact on power consumption. In some applications, it allows the CPU to spend most of its time in idle sleep mode, consuming as little as 100 nA. In a hypothetical application with eight simultaneous events of 100 kHz total frequency and 350 KBps data transfers, an 8-/16-bit MCU with an event system and DMA would be able to spend 31.9 million cycles in sleep mode and would consume a total of less than 1 mA. Any traditional 8- or 16-bit MCU without an event system and DMA would consume around 15 mA, but their performance is often too limited for these modern application types. A 32-bit MCU would consume 10.8 mA — less power than a traditional 8-/16-bit MCU, but still 20 times more than an 8-/16- bit device with event system and DMA. In an application with extensive interrupts and data, a microcontroller with an event system and DMA would consume 90% less power.

This article was written by Kristian Saether, AVR Product Marketing Manager, Atmel (San Jose, CA). For more information, contact Mr. Saether at This email address is being protected from spambots. You need JavaScript enabled to view it., or visit .