Designing a versatile data acquisition (DAQ) system begins by comparing features of the signal of interest to the capabilities of current state-of-the-art A/D converters. Specifically, signal bandwidth and maximum signal frequency are compared to the A/D maximum sampling rate and bandwidth. The specifications in Table 1 are typical of current A/Ds.
A fundamental principle of DAQ relates the minimum allowable sampling rate (the Nyquist sampling rate) to the input signal bandwidth. In order to uniquely distinguish each frequency component of the signal of interest, the sampling rate must be at least twice (in practice 3-4 times) the signal bandwidth. From Table 1 we see that theoretically, if the signal bandwidth is less than 80MHz, we can sample with a 16-bit converter at 160 MSPS. If the signal bandwidth is less than 250 MHz we can use a 12-bit A/D, and if it’s less than 1500 MHz we must use an 8-bit A/D.
The first trade-off in DAQ is apparent as an increase in signal bandwidth typically necessitates a reduction in converter resolution and SNR. The higher the sampling rate of an A/D converter, the more difficult it becomes to convert each sample with high precision. An efficient and versatile DAQ system, therefore, allows a choice of several different A/D converter front ends so that resolution (SNR) can be maximized without changing the “back-end” (post A/D) processing, allowing redeployment of the DAQ system in a new application while leveraging existing embedded processing algorithms and host software.
In the simplest DAQ system (Figure 1, top), the input signal is converted to baseband and the A/D converter samples at least as fast as the Nyquist sampling rate. That is, we have at least two (and preferably 3-4) samples per cycle of the maximum signal frequency. A low-pass filter (LPF) is used before the A/D to prevent aliases by limiting the signal bandwidth to less than half the sampling rate.
Another paradigm (Figure 1, middle) is to “undersample” the input signal, that is to sample at a rate less than the Nyquist frequency. This is known as sub-Nyquist (or IF) sampling. Consider the scenario of a typical 12-bit A/D having a maximum sampling rate of 500 MSPS and an input bandwidth of 1400 MHz. We can directly sample a signal with frequencies from 1000 MHz to 1200 MHz at a 500 MSPS sampling rate. To do this we must insure that we bandpass filter (BPF) the input signal before the A/D to prevent aliasing. The 1000 MHz will be downsampled to DC as we are sampling it once every other cycle at the same point on the waveform. The 1200 MHz signal will be downsampled to 200 MHz. The BPF insures that DC and 200 MHz (and all other aliases) are not presented to the A/D, so that we can uniquely determine each frequency component. Exploiting this situation, a DAQ system can use a high resolution, high bandwidth A/D that does not sample at a high frequency, reducing the acquisition rate and increasing SNR. A versatile DAQ system allows adjustment of the sampling rate (to control the frequency location of the downsampled signal) and allows for differing frontend filters as the center frequency of the signal changes from one application to another.
A third scenario (Figure 1, bottom) uses an ultra wideband pre-sampler before the A/D to greatly increase the effective input bandwidth of the DAQ system. Here an ultra-high bandwidth sample-and-hold is used before the A/D. The sample-and-hold has a large input bandwidth (a narrow sampling aperture) and a much lower output bandwidth (an analog output, proportional to the input during the time the aperture was open, that is held steady for a much longer time). The pre-sampler may or may not run at the same frequency as the A/D; by changing the presampler sampling rate we can position the downsampled signal in an ideal place in frequency spectrum before the A/D. We can also keep the A/D sampling rate near its maximum sampling rate so as to maximize the allowable signal bandwidth.
Information Extraction, Signal
Processing, Data Storage If the input signal bandwidth is large, we have the requirement for a high sampling rate, imposing the need for either an embedded processing engine that can keep up with the acquisition data rate and suitably reduce the data or, alternatively, a large high-speed memory to store the rapidly incoming data for subsequent processing. For many continuous real-time DAQ applications, embedded processing in an onboard FPGA can keep up with the incoming data rate, effectively reducing the data rate later sent to the high-speed memory or host bus. Even if the processing engine can keep up with the incoming data, a high-speed multi-gigabyte memory is nevertheless often required for storage of coefficients for processing algorithms, storage of reference signals for signal comparison, storage of processed signals, and to act as an elasticity buffer to prevent overruns.
By reducing the output data rate to less-than or equal-to the host bus throughput we can greatly increase the storage capacity of the DAQ system by using the host system RAM. If the output data rate is comparable to the transfer rate of a magnetic disk (several hundred megabytes per second), then a RAID can be used to increase the storage capacity by orders of magnitude, to many terabytes.
A Working Example
Having considered the desired features of a versatile DAQ system, we now introduce an example of one such system. Ultraview’s line of PCIe DAQ add-in cards support continuous DMA rates of approximately 1GBps into the host system’s RAM, have up to 8GB of on-board memory, and the option of any 1136 pin Xilinx Virtex 5 FPGA (Figure 2). These boards can capture and process data at over 6GBps while simultaneously streaming data across the PCIe bus.
These boards support dual 8-bit 3000MSPS, dual 12-bit 500MSPS, dual 14-bit 400MSPS or dual 16-bit 160MSPS A/D converters as well as custom frontend circuitry including downconversion mixers or samplers, filtering, and gain circuitry. Modular, well partitioned, VHDL firmware accommodates different front-ends by swapping existing modules and recompiling, and allows the designer to easily incorporate data processing firmware optimized for his/her application. A host uploading feature facilitates remote reconfiguration of the FPGA to change processing algorithms, or install bug fixes, without sending a technician to the field.
Ultra-Wideband DAQ, Pre-Samplers and Interleaving
Ultraview has consistently focused on high-bandwidth DAQ systems with multigigabyte deep memory, for acquiring wideband signals for long periods of time. A collaboration with Furaxa Inc. has yielded low-cost, ultra high bandwidth, sample-and-hold circuits that dramatically increase the input bandwidth of a DAQ system. These integrated circuits are installed onto an analog mezzanine and are placed before the A/D in the signal path. These ICs contain ultra wideband Rapid Automatic Cascode Exchange (RACE) samplers, some with input bandwidths over 100 GHz. These sample-and-hold ICs create sampling apertures sufficiently narrow that rapidly changing signals appear relatively constant in the several picosecond time that the aperture is open. The sample value is then held at that constant value while the lower bandwidth A/D converts the held output. These ICs have two held outputs that can feed interleaved A/Ds. This not only increases the input bandwidth of the DAQ system, but also the sampling rate, resulting in a dramatic increase in input bandwidth (maximum input signal center frequency) as well as a doubling of the maximum IF bandwidth (the signal bandwidth).
These ICs also contain an embedded wideband RACE pulser that acts as a comb signal source that can also be used as an upconverter for D/A boards. One existing application uses these ultra wideband sampler/pulser ICs for spectroscopy. Figure 3 shows the time and frequency domain plots of a Time Domain Reflectometry (TDR) system using one of these ICs.
The relentlessly increasing demand for faster real-time acquisition and more complex processing of ultra high bandwidth analog signals is being met by new data acquisition boards combining microwave pre-samplers, pre-filters, interleaved A/D converters, host-reconfigurable FPGAs, multi-gigabyte deep onboard memory buffers and high-throughput host bus interfaces. The resulting combination of high speed analog pre-processing, A/D conversion, and onboard digital post-processing enable such data acquisition systems to take in very complex RF, IF and baseband signals and either store the information in deep onboard RAM or, where possible, distill the information down to a data rate that the host system can accept on a continuous basis.