Computer-on-Module Express (COM Express) has become a widely accepted way to implement embedded computing solutions in a very compact form factor. The main principle of the COM Express standard is to implement the processor and memory on a small module (basic module size for the type 2 specification is 125 × 95 mm) and then implement specific functions and interfaces for a particular application on the baseboard.

Module and Baseboard Power Supplies

Figure 1. COM Express module and baseboard power architecture.

The power supply implementation for a COM Express module and baseboard needs careful design attention to achieve reliable designs that operate correctly in all circumstances. Figure 1 shows a typical power architecture for a COM Express module and baseboard configuration.

The combined module and baseboard design must allow for the high power consumed by the module CPU at peak maximum loading, which can be as much as 50W or more. This high power requirement is due to the high currents flowing into the CPU on the module. Having such power dissipated in such a small space can also cause thermal design challenges. Regulators on the module require high-efficiency to avoid excessive thermal dissipation, which would lead to long term reliability issues or cause problems for extreme-rugged designs that need to operate at high temperatures. The power switching regulators on the module, therefore, need careful design and component selection. For multi-core processors, particular attention should be paid to the periods when the various cores activate because there are large instantaneous changes in the loading conditions. Processors using the Intel Mobile Voltage Positioning 6.5 specification also require careful control of the power environment.

Power regulator PCB layout design is very important on a COM Express module. This includes using tracks of appropriate widths and using copper layers of the necessary weight to handle the high current flows. It is important, also, that the power IC manufacturer’s recommendations are closely followed to avoid problems. If a system designer chooses a pre-existing COM express module, power supply design issues will have been addressed by the module manufacturer. However, the high power flowing in the module should always be kept in mind when designing the baseboard. The baseboard design for the high power 12V rail is often relatively straightforward and typically transfers the supply from an input power connector to the COM Express module connectors. Careful attention to inrush current at power-up is needed in the baseboard and module design to avoid stressing components excessively and to achieve reliable module boot-up under all circumstances.

The current COM.0 standard supports an external supply into the module of +12V ±5%, but for many real-world applications, particularly for rugged designs, there is a need to support a much wider input supply voltage, for example from +9V to +16V. There is, therefore, a design decision of whether to use a module that has this wider input supply rail tolerance built in, or to implement a power regulator on the baseboard that locally generates a true +12V supply to power the module. In general, using a module with a wide input supply range is the preferred option because the module design has then been extensively tested and proven under all operating conditions.

A significant complexity of the baseboard design power section is that it needs to implement a number of regulated voltages for the various interface devices that are located on the baseboard, with their corresponding supply rails. This generally requires a number of power regulators that must all be power sequenced correctly for consistent behavior of the baseboard solution. A common problem with module and baseboard compatibility is achieving the correct power sequencing of these baseboard regulators under all conditions. If this is not done correctly it can lead to the module having boot behaviors which are difficult to debug, and in the worst case, being unable to boot reliably at all.

The presence of a 5V standby is not a requirement of the COM.0 standard for COM Express. Both ATX and AT style power supplies can be used, but if an ATX style standby supply is used it may need to support up to 2A because of all the devices requiring standby power that could potentially be implemented on the module and baseboard. Pullups to the various baseboard devices need careful attention, particularly with so many I/O interface power supplies used, and the pullups must connect to a supply that is active in the power state that the pullup itself is required to be active in. This requires careful evaluation of each of the system’s S0 to S5 states to avoid any issues with pullups during power state transitions or power sequencing.

Serial-bus Implementation

Figure 2. SIO Implementation on a baseboard with an LPC interface to the module.

The modern design approach to implementing buses between computer modules is to use high-speed serial buses such as USB, SATA, Ethernet, and PCI express. For COM.0, these buses are all available on the module connector to connect to the baseboard. Both the module and baseboard PCB layouts of these serial buses are very important, because only part of the overall serial bus circuit is implemented on the module; the other part of the circuit is on the baseboard. Both parts, therefore, need to be well implemented for successful results. For the overall serial bus circuitry layout, the design guides provided by chip vendors are helpful but they are often aimed more at single board computer designs with all bus components located on one board, or systems where the bus slots for devices are precisely defined. The COM Express module design needs to inter-operate with a wide range of possible baseboard designs and, therefore, the module layout needs to be very tightly specified by the module supplier.

Module serial bus design needs to pay close attention to providing a good layout of high-speed differential pairs, particularly in terms of controlling track impedance to within specific constraints, correct use of ground-planes, length-matching the differential pair elements, controlling impedance through the connector to the baseboard, following good routing practices, and being mindful of PCB stack-up design. Otherwise there will be issues with high-speed signal quality and the signal integrity of the bus signals, and the overall system will most likely face reliability problems that will be difficult to debug and resolve.

Because of the small physical size of the module, a large proportion of the physical bus itself is often implemented down on the baseboard, meaning additional baseboard layout complexities dealing with routing near the module connectors. Fortunately, detailed layout guidelines exist for implementation of all the serial buses used by COM.0. As long as these are followed, the baseboard implementation will be successful.

Legacy and Non-Legacy Issues

A key benefit of the COM Express module design is the plug-and-play architecture of the standard, which means that next-generation processor and RAM technologies can be quickly deployed and implemented directly onto existing baseboard designs. But in the real world, there are some problems that are typically encountered, such as plugging in a different vendor’s new generation module into an existing baseboard that is known to work, but is now unable to boot up to the OS. Some of these cases are due to BIOS compatibility issues between the module and baseboard. A particularly common example is connected with the Super I/O (SIO) solution.

The COM.0 standard defines a legacy-free implementation; this means that some of the widely used interfaces from the original PC standard are not directly supported as interfaces between the module and baseboard. Some examples of these interfaces are the keyboard, mouse, floppy disk, and serial and parallel ports. The thinking behind this change is that COM Express provides USB interfaces, and keyboard and mouse are already migrating over to USB interfaces. The floppy is going away altogether, replaced by USB memory devices. Likewise, serial and parallel ports can be implemented if needed by USB or by PCI or PCIe solutions using the available PCIe ports of COM Express. However, in real world existing applications there are still many designs that need to implement these legacy functions using the traditional PC approach. For example, some applications need very low latency on the serial port, and the extra delays in the USB interface often make USB-to-serial converters unworkable for such applications. For these relatively common legacy requirements an SIO chip is a convenient, low-cost solution.

When an SIO is used with COM Express it is located on the application specific baseboard — not the module — and the interface between SIO and module is via the LPC module interface, which is provided as standard in COM Express, as shown in Figure 2.

It is important to note that the SIO still needs to be initialized by the BIOS, even though the device itself is located on the baseboard. With a traditional BIOS, this is quite difficult in practice. A module designer does not know the baseboard application or what kind of SIO solution is included, so the module implementation needs to provide a number of different choices for this. Typical chip design choices for the Super I/O are the Winbond W83627, ITE IT8718, and SMSC 3114. Because support requirements in BIOS for each of these Super I/O devices are different, the BIOS needs to be specifically designed to work with these different SIO chip solutions. In real-world engineering implementations, supporting multiple different cases like this in BIOS written in assembler code is complex. Using an EFI BIOS can improve implementation because of the generally improved concept of EFI for device drivers.

Current and Future Directions

The latest multi-core processor technologies have more complex power requirements, with more power rails and higher powers. This affects the module power section discussed earlier. In particular, the continuously improving graphics capability requires more power to supply the graphics core, so in the future power sections will require more — and higher rated — components. Physical data security is becoming a key requirement for many applications, so a Trusted Platform Module (TPM) function is becoming more common as a requirement that needs to be added in as a component. Usually this is added to the module for security reasons. Solid-State-Disk (SSD) solutions for the bootup OS or storage of data in applications that must be immune to vibration/shock are another feature that will likely become part of the module design. The CPU and chipset ball-to-ball size is also getting smaller for the latest generation devices, and blind and buried via and via-in-pad solutions are becoming more commonly used, leading to more complex PCB fabrication requirements for module manufacturers.

Serial bus speeds are constantly evolving and increasing in order to support higher throughput. For example, SATA has increased from SATA 1.0 at 1.5 Gbps, through SATA 2.0 at 3 Gbps, to SATA 3.0, which uses 6 Gbps. High-performance flash drives are already approaching the 3 Gbps transfer rates (SATA 2.0), so the 6 Gbps of SATA 3.0 is likely to become more of a requirement in high performance COM Express applications. USB also is moving to higher speeds from 2.0 to the future USB 3.0. PCI express already supports 2.0 with a 5 GHz clock speed. Overall, at these bus speeds the performance of the module connector itself starts to affect bus performance, making bus signal integrity more challenging to achieve.

Many baseboard designers are using FPGA solutions to control power-up sequencing, making module compatibility quite complicated to achieve. Guaranteeing correct operation in all circumstances is difficult when the action of FPGA code also needs to be taken into account.

COM Express uses the COM.0 standard to define the processor based module features, but as technology changes and new interfaces are developed, there are difficulties making the standard work in a fully compatible way. For example Intel’s latest Calpella platform provides for two SPI devices, DisplayPort, and dual channel NAND interface, but the existing COM.0 definition does not include these features. To overcome this limitation the designer needs to use reserved pins on the module connectors, but this leads to compatibility issues with other existing modules. Future interface technologies may lead to further updates of the COM.0 standard to define new module types that support these interfaces. The large number of resulting module types may then make straightforward module interchangeability more challenging to achieve.

This article was written by Dr. Qi Chen, Sr. Director of Engineering, Ampro ADLINK Technology, (San Jose, CA). For more information, contact Dr. Chen at This email address is being protected from spambots. You need JavaScript enabled to view it., or visit

Embedded Technology Magazine

This article first appeared in the May, 2010 issue of Embedded Technology Magazine.

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