Imec (Leuven, Belgium) has demonstrated 3D integrated DRAM-on-logic for lowpower mobile applications. The 3D stack technology consists of Imec’s proprietary logic CMOS IC, on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps. Heaters were integrated to test the impact of hotspots on DRAM refresh times. The chip contains test structures for monitoring thermo-mechanical stress in a 3D stack, electro-static discharge (ESD) hazards, electrical characteristics of TSVs and micro-bumps, and fault models for TSVs.

Imec’s 3D integrated DRAM-on-logic demonstrator showed that a minimum die thickness of 50μm is required to deal with local hot spots on the logic die, which are generated by local power dissipation. Due to the strongly reduced lateral heat spreading capability of thin die, these hot spots are higher in temperature and more confined if the die thickness is reduced.

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This article first appeared in the April, 2012 issue of Embedded Technology Magazine.

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