The Virtex®-7 X690T FPGA device from Xilinx (San Jose, CA) uses 80 GTH serial transceivers that run up to 13.1 Gbps to break the 2 Tbps single FPGA bandwidth barrier. The FPGA enables scalable chip-to-chip serial interfaces, 10GBASE-KR backplanes, and high signal-integrity interfaces. To accelerate design and debugging, each GTH transceiver also includes a nondestructive, high-resolution 2D eye-scan circuit that allows designers to see and measure the receiver eye from within the FPGA. By leveraging the advanced 7 series FPGA architecture built on the TSMC 28HPL process, the new device can save more than 25 percent total power over similar density FPGAs.

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Embedded Technology Magazine

This article first appeared in the August, 2012 issue of Embedded Technology Magazine.

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