System in Package (SiP) designs from Endicott Interconnect Technologies (Endicott, NY) bring multiple packages from a printed wiring board (PWB) into a SiP for improved electrical performance, and reduced PWB complexity and cost.

Endicott Interconnect (EI) can use its SiP technology to achieve reductions in PC board real estate by up to 27x less than that of the original PCB using reduced package size components and PTFE-based HyperBGA® or CoreEZ™ organic semiconductor packages featuring thin core build-up flip chip technology. For example, a 7.75" x 15" PCB can be redesigned to a 2.2" x 2.2" size using a 3-4-3 CoreEZ substrate with 4 signals, 6 planes, and 30 micron lw/ls, and an assembly that includes 5 flip-chip FPGAs, CSP memory, passive components, SMT components, PGA connector and 2-sided assembly. Another SiP conversion condensed a single board computer design from 25 sq. in. to 9 sq. in. EI's SiP designs are not physically limited to a square or rectangular shape.

To achieve substantial reduction in PWB design complexity and cost, elements include organic substrates for significant weight reduction, thin substrates for significant electrical performance improvements, SiP designs for shorter signal paths, and pinned or BGA PWB interface.

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Embedded Technology Magazine

This article first appeared in the January, 2008 issue of Embedded Technology Magazine.

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