VMETRO FPE650 FPGA processing engine

The FPE650 from VMETRO (Houston, TX) is a FPGA processing engine with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard. The FPE650 integrates four Xilinx Virtex-5 FPGAs with two FMC I/O sites and VPX high-speed serial backplane connectivity, allowing I/O and processing capabilities in a single 6U slot. The FPE650, available in air-cooled and conduction-cooled rugged versions, tackles demanding digital signal processing applications such as electronic counter measures (ECM), signal intelligence (SIGINT), and electro-optics (EO).

The FPGAs' sites can be fitted with Virtex-5 SX95T, LX155T, or FX100T platforms enabling the FPE650 to be optimized for DSP or logic centric designs. Two of the FPGAs interface to four banks of 9 Mbytes QDR2 SRAM memory and the other two FPGAs interface to two banks of 9 Mbytes QDR2 SRAM memory and two banks of 640 Mbytes DDR2 SDRAM memory.

The FPE650 addresses I/O and data bandwidth requirements with three interconnects features: through FPGA Mezzanine Card sites for front panel I/O, through a non-blocking crossbar to help optimize the FPGA topology, and VPX/VITA 46 connections for backplane I/O. For front panel I/O, each FMC site has 68 differential signal pairs supporting 2Gb/sec data rates per pair and four full duplex multi-Gigabit/sec connections to enable very large amounts of data to be moved between FMC modules and the on-board FPGAs. For backplane I/O, each FPGA has two x4 full duplex multi-Gigabit/sec serial ports routed to the VPX backplane with each x4 port able to move over 1 Gigabyte/sec of data.

For Free Info Click Here 


Embedded Technology Magazine

This article first appeared in the July, 2008 issue of Embedded Technology Magazine.

Read more articles from this issue here.

Read more articles from the archives here.