An advanced technique of deep reactive-ion etching (DRIE) has been developed for fabricating smooth vertical walls in silicon wafers. These walls are suitable for use as bounding surfaces of optical waveguides in photonic and optoelectronic devices. The roughness of a typical 8-µm-high vertical wall surface of a waveguide made by this technique is <20 nm; by keeping the roughness at such a low level, one helps to ensure that the waveguide is capable of low-loss optical transmission.
The specific DRIE technique, denoted the "Bosch" technique, involves repeated exposure of a photoresist-masked silicon wafer to (1) an etchant (SF6 + C4F8 ) plasma in alternation with a passivant (C4F8) plasma. To ensure vertical, smooth walls, it is necessary to investigate, in detail, the effects of variations in all photoresist and DRIE process parameters and then to exert tight control over these parameters. Among other things, this means that the photoresist process parameters must be chosen to obtain perpendicular photoresist side walls. The power levels of the plasma apparatus in the etching and passivating steps, the durations of these steps, the total number of etching-and-passivating cycles, and the pressures and rates of flow of the SF6 and C4F8 gases must also be investigated in detail and then controlled to obtain vertical walls with low roughness.
Ranges of parameters that have been investigated in a DRIE apparatus at NASA's Jet Propulsion Laboratory are the following:
- Total process time - 10 to 30 minutes;
- Pressure - 5 to 40 millitorr (0.7 to 5 Pa)
- Durations of etching and passivating steps - 4 to 10 seconds;
- Rate of flow of SF6 gas during etching step - 100 to 180 standard cubic centimeters per minute (sccm);
- Rate of flow of C4F8 gas during etching step - 30 to 70 sccm;
- Platen power during etching step - 12 to 16 W;
- Coil power during etching step - 575 to 650 W;
- Rate of flow of C4F8 during passivating step - 90 to 140 sccm;
- Platen power during passivating step -0 to 2 W;
- Coil power during passivating step - 575 to 650 W.
This work was done by Chi Wu, Stephen Vargo, and Tasha Turner of Caltech for NASA's Jet Propulsion Laboratory.
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Reactive-Ion Etching of Smooth Vertical Walls in Silicon
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