Vertical-Bloch-line (VBL) memory devices of a proposed type would include stacks of VBL memory chips plus other components (see figure on next page). Each chip would be square, approximately 15 mm on each side. Each chip would have two input/output (I/O) lines connected to 16 I/O pads on each of two opposite edges. All the chips in a stack would be oriented with their I/O pads on the same two opposite faces of the stack. Buses for connection to external circuitry would be positioned to cross the chip edges on these two faces, making contact with the I/O pads.

As specified in a preliminary design, the core of each VBL memory chip would comprise 512 VBL storage loops with 2,048 bits per loop. Thus, each chip could store 512×2,048 = 1,048,576 bits. The storage loops would be embodied by stripe domains stabilized in main grooves 5µm wide and 1.25 µm deep in a garnet substrate. The bits would be embodied by VBL pairs in the walls of the stripe domains and would be stabilized by grooves 5 µm wide and 0.125 µm deep perpendicular to the main grooves. This design would make it possible to exchange 16 32-bit data with the core in parallel. With refinements in design and fabrication involving primarily the use of readily available 2-µm magnetic-bubble material and narrower features (viz., storage loops and I/O lines 2 µm wide and bit grooves 0.5 µm wide), the storage capacity of a chip of the same size could be increased to about 25 Mb. Then using submicron lithography when the 0.5-µm magnetic-bubble material now undergoing development becomes available, it should be possible to increase the capacity to about 400 Mb per chip.

VBL Chips Would Be Stacked to obtain high bit density in a memory device. The general design of devices like this one reflects consideration of manufacturability, yield, biasing, driving, and packaging

In addition to I/O drive currents supplied via I/O pads, operation of a VBL chip depends on two spatially uniform magnetic fields perpendicular to the chip plane: a dc magnetic bias field and field oscillating at a frequency of several megahertz for VBL propagation. In a device as proposed, the dc magnetic bias fields would be provided by permanent-magnet plates between the chips and at the ends of each stack. The high-frequency VBL-propagation magnetic field would be generated by use of a coil surrounding the stack.

Nonuniformity in the dc magnetic field at the ends of the stack could be reduced to acceptable levels by stacking more magnets at the ends, thickening the end magnets, using high-permeability equalizer plates, bevelling the edges of the magnets to reduce edge fields, and/or the use of a high-permeability sheet housing that would both perform the function of a conventional magnet yoke and act as a shield against externally generated magnetic-field disturbances. The number of windings in the VBL-propagation coil must be large enough to keep the nonuniformity of its magnetic field acceptably small, but not so large that the resulting inductance would be excessive at the operating frequency. The optimum winding density would probably be about 1 turn per chip, except at the ends, where the winding density would have to be doubled to prevent excessive nonuniformity of the magnetic field.

This work was done by Udo Lieneweg of Caltech for NASA's Jet Propulsion Laboratory. For further information, access the Technical Support Package (TSP) free on-line at under the Electronic Components and Systems category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Technology Reporting Office JPL Mail Stop 122-116 4800 Oak Grove Drive Pasadena, CA 91109 (818) 354-2240

Refer to NPO-20151, volume and number of this NASA Tech Briefs issue, and the page number.

Electronics Tech Briefs Magazine

This article first appeared in the April, 1999 issue of Electronics Tech Briefs Magazine.

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