Sarnoff Corporation has announced the development of four new analog-to-digital (A/D) converter macro cells for embedding in CMOS designs in which high-precision, high-speed operation at low power is important. The 8-bit, 10-bit, 12-bit, and dual 6-bit designs are available for licensing by manufacturers who need A/D conversion modules as elements in new very large-scale integrated (VLSI) designs, or who want to upgrade their converters in existing designs. The A/D converter macro cells have extensive applications in video, audio, and wireless signal processors. They are designed with low power requirements, small areas, and mainstream CMOS compatibility and scalability for ease of embedding into VLSI digital signal processing (DSP) chips.
Typical features and specifications include:
- for the dual 6-bit cell, speed of 60 MHz; power of 80 mW, 3.3 V; size of 1.3 × 0.9 mm; and process of 0.35 micron;
- for the 8-bit flash, speed of 60 MHz; power of 145 mW, 5.0 V; size of 1.3× 1.2 mm; and process of 1.0 micron;
- for the 10-bit, speed of 40 MHz; power of 200 mW, 3.3 V; size of 2.7 ×4.0 mm; and process of 0.5 micron;
- for the 12-bit, speed of 20 MHz; power of 250 mW, 5.0 V; size of 6.4 ×6.4 mm; and process of 0.6 micron.
The dual 6-bit design and the 10- and 12-bit designs all use a patented successive approximation register architecture and MOS servo-loop circuitry to achieve high speed and high precision. The servo loop's auto-zero and auto-calibrate circuits function during each conversion cycle, eliminating the need for the usual precision component trimming or matching.
The 8-bit flash converter uses an "average interpolating" approach to reduce power requirements and boost speed. All four A/D converter macro blocks accept TTL inputs and provide CMOS or TTL outputs. They also feature tri-state output buffers with enable. The converters combine precision and performance without the complexity of bipolar or BiCMOS technology.