Part 1 of this article introduced a phenomenon called power-on/off glitch. The example discussed the impact of this phenomenon on a motor control system. We limited our analysis to a DAC where the output buffer is powered on in normal mode: zero-scale or mid-scale. In Part 2, we analyze when the DAC output is powered on in high-impedance mode. We present a mathematical model for the power-on glitch, followed by board-level solutions to minimize it.
This analysis pertains to DACs where a power-on glitch reduction (POGR) circuit is absent. Part 1 tabulated factors that impact the power-on/off glitch. When the DAC powers on to high-impedance mode during supply ramps, the power-on/off glitch also can be seen as a transient charge buildup on the DAC’s voltage output (VOUT) pin. This charge buildup is a result of capacitive coupling from the supply pins to the VOUT pin via parasitic capacitances inside and outside the chip. Note that compared to the power-on glitch (Part I), this glitch is AC in nature. Thus, its magnitude depends on the power supply ramp time. In most multi-supply chips, the digital supply and reference pins have a weak parasitic path to the VOUT pin. Therefore, these pins are not dominant contributors to power-on/off glitches.
The NFET/PFET transistors in a DAC’s output stage are much larger versus other switches because the output stage is designed for a certain load drive. Therefore, parasitic capacitances of these FETs are much higher than other on-chip components. Figure 1 shows a simplified diagram of a typical precision DAC’s output stage (DAC8760). This diagram assumes separate power supplies for output stage and the chip’s digital core. The diodes on the feedback node are placed to protect the transistors in gain/power down network.
The dominant parasitic capacitance as seen into the VOUT pin is a combination of parasitic capacitance of the VOUT bond wires, leads, and output FETs. With this assumption, the DAC output pin can be modeled as a simple capacitive divider. The simplified model in Figure 2 uses two diodes between feedback node and VREF/AGND. Since these diodes represent a FET (Figure 1), the drop across these diodes is negligible and is ignored in further analysis.
The feedback resistor (RFB) and FETs placed between the feedback node and VREF/GND place an upper and lower limit on the glitch’s magnitude. The maximum power-on/off glitch that can be observed in this condition is limited between VREF and GND.
Assuming that the supply ramp time for AVDD and AVSS is identical, we can divide this glitch (VOUTGL) into two regions:
Where VOUTGL is the magnitude of the glitch, CPARP, CPARN, and CL are the parasitic and load capacitances, respectively. AVDD/AVSS = power supplies, VREF = reference voltage, RL = load on the VOUT pin, RFB = feedback resistor inside the chip, and dt = ramp time for AVDD/AVSS supply.
The maximum negative power-on/off glitch is limited within a diode drop of AGND. For example, the typical value of CPARP and CPARN is ~150 pF. Using a single supply operation where AVSS = 0V, AVDD = 15V, VREF = 5V, RL = 50 MΩ, and dt = 70 msec, the glitch amplitude is calculated as ~1.5V. Figure 3 shows the measured plot of a power-on/off glitch under these conditions for DAC8760.
Minimizing Power-On/Off Glitch
Let’s explore some methods to minimize the power-on/off glitch. From equations (1) and (2), we see that some terms in these equations are constant. For example, the parasitic capacitances are a function of the device parasitics. Supply voltages are determined by the application requirement. Ramp time is determined by the power supply design. The only terms left are load impedance and sequencing of VREF with respect to supplies. This leads to two main methods of reducing power-on/off glitch: supply sequencing and load.