Power-on glitches do not depend on the state of DAC registers. All DAC registers are held in reset state while the DAC powers up by a circuit called power-on reset (POR). By the time these registers are released from the reset state, the output and pre-output stages have enough headroom to function correctly.
A simple supply detect circuit (Figure 3) can be used to load the DAC’s output momentarily during supply ramp-up. The DAC output VOUT is loaded with resistor RL during the supply ramp-up via FET MPD. The supply-detect block generates the MPD control. During the supply ramp-up, the control signal CTL is pulled to AVDD loading the DAC output VOUT with load RL until the FET MN1 is turned on. After MN1 is completely turned on, it pulls CTL node to ground, unloading the VOUT node. R1, R2, R3, and CL must be sized according to the threshold voltage of MN1.
This article analyzed the power-on glitch and its root causes. While most of the analysis addresses power-on glitches, the same principle applies to power-off glitches. Certain DACs power on in normal mode with no internal POGR circuit. A small resistive load between the output pin and ground during startup is the only way to minimize the power-on glitch of these DACs.