A complementary metal oxide/semiconductor (CMOS) focal-plane readout circuit for an imaging array of long-wavelength infrared (LWIR) photodetectors effects in-pixel current-mode subtraction of the dark-level component of each photodetector output. The dark-level signal is subtracted before the signal reaches the integration node. Consequently, for each pixel in the array, the readout noise is minimized and the net gain and dynamic range are maximized.

This readout circuit was designed to overcome two major obstacles to the achievement of high performance in LWIR arrays used in imaging or spectroscopy under common operating conditions:

  • Leakage in the photodetectors and/or high scene background gives rise to a large background signal, making it necessary for the focal-plane circuitry to handle of the order of several billion electron charges per pixel per readout cycle. Ordinarily, prohibitively large capacitors would be needed to handle such large amounts of charge, and the handling of large amounts of charge would introduce additional noise.
  • Often, there is poor signal-to-background contrast in the sense that the signal of interest is of the order of only 10-4 or 10-3 times the background signal.

The present circuit operates in a readout cycle in which a blanking or calibration phase alternates with an imaging phase. During the blanking phase, a current-memory circuit memorizes the background current for use in predicting the background current for the subsequent imaging phase. During the imaging phase, the current-memory circuit acts as a high-impedance current source that generates the predicted background current, which is subtracted from the photodetector output current to obtain the signal current of interest. This signal current is coupled to external circuitry through low-noise circuitry, and an innovative biasing scheme improves low-noise performance.

Each Unit Cell of the Readout Circuit effects in-pixel current-mode subtraction of the dark-level component of each photodetector output prior to integration.

A prototype of the circuit comprises a bilinear array of 2 × 132 multiplexers. Each unit cell (see figure) contains a LWIR photodetector [more specifically, a quantum-well infrared photodetector (QWIP)], a buffered-direct-injection (BDI) input circuit, a current-mode pedestal-subtracting circuit, and a voltage-mode double-sampled differential readout (DSDR) circuit. The BDI input circuit provides the stable bias needed for operation of the QWIP, plus a high input impedance that enables high quantum efficiency. The current-mode pedestal-subtracting circuit comprises a cascode current-memory circuit, and an isolation field-effect transistor (FET) denoted "Mread."

During the blanking phase, the current Ibak flowing through the QWIP consists of the detector dark current (usually the dominant component, of the order of a few hundred nanoamperes) plus a smaller current due to scene and instrument background. Ibak is the pedestal signal that one seeks to subtract. Ideally, once the current-memory circuit has memorized Ibak, it should be able to generate Imem = Ibak. However, because of imperfections in the circuit, Imem and Ibak differ by a small amount: Imem = Ibak Ires, where Ires is denoted the error current. The pedestal signal due to Ires cannot be eliminated in the current-mode subtraction; therefore, it is estimated in the voltage mode by integrating the error current onto capacitor CR in the DSDR circuit. This completes the memorization of the background signal.

During the imaging phase, the current through the QWIP rises above Ibak by an amount Isig, which represents the infrared signal to be measured. Thus, the current sent to the integration node during the imaging phase equals Isig + Ires. Once the imaging phase has been completed, the voltage Vint obtained by integrating Isig + Ires onto integration capacitor Cint is sampled on capacitor CS in the DSDR circuit. As a result, the difference between the potentials on CS and CR is almost exactly proportional to Isig, with background suppressed by factor of more than 104.

The gate of Mread is dc-biased with a voltage, such that during the blanking phase, the current-memory potential shuts Mread off, while during the imaging phase, the source of Mread charges up to a potential that enables the injection of current into the integration node. This biasing scheme makes it possible for the circuit to operate without need to apply a pulse signal fread to Mread. In so doing, the biasing scheme helps to keep noise low by preventing the injection of switching noise into a sensitive node.

The circuit provides for noise-limited measurement of signals 85 dB below the dark level. It is designed to operate with low power dissipation and high linearity, and is capable of handling pedestal currents up to 300 nA. Accurate subtraction of background charge makes possible a charge-handling capacity of >5 ×109 electron charges per pixel.

This work was done by Bedabrata Pain, Guang Yang, Chao Sun, Timothy Shaw, and Chris Wrigley of Caltech for NASA's Jet Propulsion Laboratory.

NPO-20486