Advanced driver assistance systems (ADAS) are improving driver and pedestrian safety, providing vehicle capabilities such as pedestrian detection, lane departure warnings, collision avoidance, and much more. The increasing use of cameras throughout vehicles is enabling many ADAS capabilities. For ADAS applications involving cameras, one critical design challenge is to move image data from the camera to the processing unit and from the processing unit to each display as quickly and efficiently as possible.

Figure 1. ADAS block diagram

When designing ADAS camera systems, there are some key factors to be aware of:

  • Bandwidth — Depending on its purpose, performance demands are different for each camera. For example, a back-up assistance camera with wide-angle lens may require 1.3 megapixels with 18-bit color per pixel at 30fps. Factoring in the control bits and encoding for balance, this single camera would generate >1Gbps of data.

  • Latency — A vehicle travels 91.13 ft (27.8m) every second when moving at a speed of 62.5mph (100km/hr). Obviously, when it comes to passenger and traffic safety, every second counts.

  • Reliability — To ensure that the vehicle continues running smoothly, it's essential to be able to adapt to wear and tear over the vehicle's lifetime and to detect when service is required.

  • Power consumption — As the number of electronic systems in vehicles continues to grow, staying within battery capacity and distribution constraints becomes increasingly difficult.

  • Cost — To keep system costs low and the technology competitive, it's important to find ways to reduce the number of components and cables in vehicles.

  • Image quality — High-quality images are critical for ADAS applications that are based on vision-based object detection.

Serializer-deserializer (SerDes) technologies can enable high-performing camera systems with robust, compact, and flexible communication links. This article takes a look at how these technologies can help automotive engineers design safer, smarter cars.

Gigabit Multimedia Serial Link (GMSL) SerDes Technology

Figure 2. Typical application circuit for back-up assistance GMSL SerDes systems

The right SerDes products can provide high reliability and flexibility for uncompressed camera-feed transmission systems. SerDes chipsets can take uncompressed parallel video output from an image sensor and combine it with control inputs to serialize it into a single high-speed output. The chipsets then transmit this data across a cable and convert the received signals back into the original parallel video output on the deserializer side. Many systems are designed to provide both power and high-speed bidirectional data through the same cable. The Maxim Integrated MAX967xx family is an example of a set of products that offers safety and reliability features specifically for ADAS applications:

  • Control channel error-detection and retransmission, which ensures 100% accuracy when configuring a link;

  • Crossbar switch supporting any parallel input to any parallel output;

  • Reduced EMI/EMC;

  • Enhanced cable drive with 50 coax or 100 shielded twisted pair;

  • Eye-width monitor and adaptive equalization;

  • Flexible data input up to 1.74Gbps;

  • AEC-Q100 qualification;

  • Dedicated frame sync GPO.

Crossbar Switch Eases Layout Constraints, Supports Design Reuse

By including a crossbar switch in an ADAS design, any data input can be configured to route to any data output. This eases layout constraints and enables design reuse, which could significantly cut development costs. If image sensors with different output buses are supported for a given application, all sensors can interface to the same serializer board. In each scenario, the crossbar switch can be configured to ensure that the signals applied to the serializer are routed to the appropriate deserializer output. Design time is significantly reduced by designing a single serializer board that interfaces with different camera modules. The deserializer side can enjoy the same benefit. For the combination of a single camera module and serializer, a number of different deserializer boards and graphics processor combinations can be used to interpret the incoming camera data. The increased compatibility is simply enabled via an internal crossbar switch.

Detecting Line Faults

Some parts in the MAX967xx product line provide built-in line-fault detection. By attaching an external resistor network from the serial link to the LMN0/LMN1 pins and including a reference voltage between 1.5V and 1.7V, the system can automatically detect the physical state of the serial link. An optional hardware pin, LFLTB/GPIO1, can be used to provide an alert upon detection of an open cable, short to battery, or short to ground. Two line-fault monitor pins, LMN0 and LMN1, are included for use with single-conductor coax cables and shielded twisted pair (STP) cables.

The normal operating threshold for the LMN0/LMN1 pins is 0.57V to 1.07V. If the cable is shorted to ground, the line voltage is pulled below this threshold. If the cable is open, the line voltage is pulled up to the reference voltage between 1.5V and 1.7V. If the cable is shorted to the battery, the line voltage is pulled higher than 2.5V.

Overcoming Voltage Issues in Power-Over-Coax Circuits

In many systems, one STP cable actually contains two pairs, one for power and one for data. There are some advantages to using coax cables instead of STP cables for SerDes links, however. Coax cables are cheaper, lighter, more flexible, and less lossy at high frequencies. To be competitive, low-cost coax cables must provide both power and data through a single cable. To achieve this, the available frequency spectrum on the inner conductor is divided into power, reverse-channel data, and forward-channel data bands. Filtering passes the appropriate frequency band to its corresponding circuit. A series capacitor to the transceiver inputs AC-couples the data channels.

Figure 3. Power over coaxial schematic

The DC power typically uses the low-pass quality of series inductors to construct filters whose impedance rises above 1k in the reverse-channel and forward-channel frequency bands. Since the data channels operate with 50 termination, the 20x increase in impedance is sufficient to couple the DC voltage and filter the high-frequency content. Every inductor has parasitic capacitance that causes self-resonance and a corresponding drop in impedance at high frequencies. Inductors of different sizes are therefore chosen to filter out all the bands of interest.

The current delivered across the cable must pass through each inductor in the power filter, constraining various aspects of inductor parameter selection, including saturation current (ISAT), DC winding resistance (DCR), and package size. If a current greater than ISAT flows through an inductor, the inductor saturates, and the inductance drops steeply. There is a power loss proportional to the square of the current multiplied by the inductor's DCR, which causes self-heating to occur. If the power delivery rail does not include a built-in voltage margin, then the voltage drop across the power filter may lead to insufficient voltage levels at the load.

You can avoid each of these three potential problems by applying a higher voltage to the cable, which lowers the cable current. You can also choose inductors with sufficient size and saturation current rating to manage the required cable current.

Programmable Adaptive Equalizer

Cables inherently have parasitic impedance that degrades signal quality as frequencies increase. Also contributing to signal degradation are longer cable lengths. To compensate for the low-pass nature of a transmission cable, many high-speed transmission systems place a cable equalizer at the front end of the receiver input. Equalizers amplify high-frequency signals of interest so that, when paired with the frequency response of the cable, the receiver can recover broadband signals with higher fidelity. MAX967xx deserializers feature built-in adaptive equalizer circuitry with 12 different compensation levels, allowing the SerDes system to handle up to 30m coax and 15m STP cable lengths. The adaptive equalizer can be programmed to periodically re-adapt and it can also be triggered manually to compensate for any changes in the transmission environment.

Eye-Width Monitoring Circuitry

The inclusion of eye-width monitoring circuitry can increase the robustness of high-speed communication over a long cable. Sending a pseudo-random bit sequence (PRBS) across a transmission line and plotting the transitions, generates a persistent plot that represents an eye. The transitions in an eye diagram are narrow, resulting in an open eye, when there's a stable clock and compensated cable. When cable quality decreases or cable length increases, the high-frequency content of each transition is attenuated, causing the eye to start closing. The MAX96706 features an optional monitor that senses the eye-width opening. When it senses that the eye-width is decreasing below a threshold, the monitor raises a flag on the ERRB output pin or triggers a retuning of the adaptive cable equalizer. The eye-width monitor provides added reliability to the SerDes link by constantly measuring the eye width and adjusting the system settings when performance drops.

8b/10b Encoding for Better Serial Link Quality

8b/10b encoding relies on an algorithm that encodes data for a transmission line in which each 8-bit data byte is converted into a 10-bit symbol. An 8b/10b encoded data stream has an equal number of 1s and 0s, and limits the number of consecutive 1s or 0s to 5 bits. If a transmission line isn't DC-balanced, the voltage on the line can accumulate over time, leading to bit errors. Say there's a situation where consecutive 1s are transmitted. In this case, the AC-coupling capacitors in a SerDes link will develop a DC voltage that appears incorrectly as a 0 at the receiver. 8b/10b encoding tracks the running disparity of 1s and 0s, ensuring that the next generated symbol will maintain the running disparity within ±1. Through the course of a lengthy period, the number of 1s and 0s transmitted is split 50-50.

The transmission clock is embedded in a SerDes data stream. It therefore has to be extracted from the data at the receiver. The receiver accomplishes this by monitoring the transitions that occur in the data. Long patterns of 1s or 0s disrupt the ability of the receiver to recover the clock signal. By limiting the number of consecutive 1s or 0s, 8b/10b encoding avoids this scenario.

Pixel Clock Rate Calculations

Typically, an image sensor outputs information from one pixel for every pixel clock cycle. The pixel clock for a given camera application is calculated from the image size and number of images displayed every second:

Pixel rows x pixel columns x frame rate = Pixel Clock (Hz)

When communicating from serializer to deserializer, Maxim GMSL devices internally use data widths of 24, 27, or 32 bits. 8b/10b (and 9b/10b) encoding translates these data widths into 30- or 40-bit packets that are sent across the link. While this packet encoding happens automatically and internally, you should keep this packet structure in mind when deciding how to choose a pixel clock rate and allocate the parallel data to be sent across the link.

The MAX967xx product family features a maximum serial data rate of 1.74Gbps. Given that data is sent in 30-or 40-bit packets, this translates to a maximum packet update rate of 58MHz or 43.5MHz, respectively.

Summary

ADAS applications are helping to make our roadways safer. This article highlighted how GMSL SerDes technology delivers the high reliability and flexibility for uncompressed camera feed transmission systems that are essential for ADAS applications.

This article was written by Roland Dorn, Business Director, Automotive Business Unit, Maxim Integrated. For more information, Click Here .


Photonics & Imaging Technology Magazine

This article first appeared in the March, 2018 issue of Photonics & Imaging Technology Magazine.

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