As signal rates approach 50 Gb/s, bandwidth demand has outpaced conventional circuit boards. Engineers are now turning to PAM4 signaling rather than conventional NRZ as the most viable solution to these design challenges.
Since bit error rate (BER) is the ultimate judge of signal integrity, tests of PAM4 components and systems are performed by BERTs consisting of precision pulse pattern generators (PPGs) and sensitive error detectors (EDs). To satisfy this application, the PPGs must transmit signals with specific signal impairments for receiver tolerance testing, and the EDs must serve as golden reference receivers and signal quality analyzers for transmitter testing.
As its name implies, PAM4 is a 4-level signal scheme that encodes two logic bits in each of its 4 symbols. Since each PAM4 symbol occupies the same unit time interval as an NRZ symbol, PAM4 doubles the data rate without altering the bandwidth. Each PAM4 symbol encodes a unique pair of bits, an LSB (least significant bit) and an MSB (most significant bit).
To meet these new challenges, emerging PAM4 standard specifications relax the raw BER requirements from the usual BER < 1E-12 to BER < 1E-6 without losing performance by employing FEC (forward error correction). FEC requires additional overhead of about 5.5% in parity-like bits but can correct a raw BER of 1E-6 to a net BER of 1E-15 or better.
Where NRZ test patterns are pseudorandom binary sequences (PRBS), PAM4 uses pseudo-random quaternary sequences (PRQS). PRBSn test patterns include pseudo-random combinations of n bits (a total of 2n-1 bits); PRQSm patterns have pseudo-random combinations of m symbols. PRQSm PAM4 test patterns are generated by combining two NRZ PRBSn patterns.
PRQS Test Patterns
The preferred test pattern for NRZ signals at 16+ Gb/s has always been PRBS31; PAM4 patterns are comprised of two PRBS31s. Since the pattern is more than 2 billion symbols, oscilloscopes are ill-suited for the application. The limited memory depth of real-time oscilloscopes and the low sampling rates of equivalent-time oscilloscopes prevent them from making accurate measurements on test patterns longer than a few million symbols. BERTS, such as the one shown in Figure 1, with 256 Mb of test pattern memory, support PRQS15 BER measurement of every single bit and PRQS31 BER measurement of all MSB bits.
SSPR Test Patterns
To address oscilloscope limitations, the SSPR (short stress pattern random) pattern has been proposed. It contains enough random sequences to probe the receiver performance baseline wander margins and timing content. The SSPR pattern is of limited use in serdes testing. PRQSm PAM4 patterns can be created on silicon with simple shift registers for serdes self-testing. PPGs with 256 Mbit of user-defined PAM4 pattern memory can generate a huge array of unique test patterns for probing any combination of a serdes’ AC coupling, clock recovery, equalization, and symbol decoder.
Other test patterns are used for PAM4 signal evaluation. JP03A is a clock-like sequence of alternating V0 and V3 symbols to measure CRCrms (rms clock random jitter) in transmitter tests or to calibrate it for receiver tests. JP03B consists of 15 alternating V0 and V3 symbols followed by 16 alternating V3 and V0 symbols. A clock-like sequence of alternating V0 and V3 symbols with a single pair of V3 symbols in its center can be used to measure half period F2 jitter (even-odd jitter) in transmitter tests or to calibrate it for receiver tests.
Emphasis and FFE
Eye closure due to inter-symbol interference (ISI) is caused by the channel's frequency dependent loss. Just as equalization has been used in NRZ systems to open eye diagrams by compensating for the frequency response, it is also used to open the three eye diagrams of PAM4 signals.
The simplest approximation of the channel response is a low pass filter. The idea of transmitter feed-forward equalization (FFE) is to counter this low pass effect by emphasizing high-frequency signal components.
Two-tap emphasis is the simplest form of transmitter FFE. Symbols that undergo transitions are transmitted at higher amplitudes than those that follow. Transmitter emphasis can be applied in varying amounts to any number of symbols prior to or after a transition. Most emerging PAM4 specifications require 2- to 4-tap transmitter emphasis.
Two equalization schemes are used at the receiver. A continuous time linear equalization (CTLE) applies a simple filter to suppress low-frequency signal components and amplify high-frequency components. Decision feedback equalization (DFE) feeds the decoded symbol values back through the symbol decoder to further reduce ISI.
To acquire the most accurate data, pattern generators apply PAM4 emphasis separately to the LSB and MSB NRZ data streams with a 4-tap emphasis module prior to a PAM4 converter, as shown in Figure 2. The eye-opening effect of PAM4 transmitter emphasis is shown in Figure 3.
PAM4 receivers are complex, as they have AC coupled front ends, clock recovery circuits, equalizers and three integrated voltage slicers in one unit. To diagnose hardware problems, distinct stresses are used to challenge each component. For compliance testing, all the components must be stressed simultaneously.
It's imperative for both diagnostic and compliance testing to start with pristine, instrument-quality, low SNR signals. With 12 distinct rise and fall times, it's also crucial that the unstressed PAM4 test signal have wide open eye diagrams that require sharp symbol transitions. To make accurate tests, PPGs should have rise/fall times faster than 12 ps and apply adjustable levels of every stress type required for compliance measurements of every major technology standard.
Some PAM4 receivers can count their own errors either through their FEC coding block, which is capable of counting considerably more errors than it can correct, or through internal frame loss rate (FLR) detection. Most PAM4 standards specify BER < 1E-6 or 5E-5, independent of FEC, or FLR < 6.2E-10 for 512 bit frames, including FEC. These requirements assure post-FEC performance of BER < 1E-15.
In moving from two-symbol NRZ to four-symbol PAM4 a factor of two in bandwidth is achieved. The trade-off, however is increased complexity and signal-to-noise ratio (SNR). With four levels, PAM4 signals have three distinct but not independent eye diagrams. The voltage swing between adjacent levels is no more than one third the swing between NRZ levels. This lowers the SNR by at least 9 dB from what is typical with NRZ signals. For this reason, a BERT ED should serve as a golden reference receiver and signal quality analyzer when analyzing PAM4 signals.
BERT EDs must have excellent sensitivity to make accurate measurements of the high SNR, low voltage-swing PAM4 eye diagrams. ED sensitivity is the smallest voltage swing for which the ED can distinguish symbol levels. For PAM4 measurements, ED sensitivity should be typically 10 mV.
BERT EDs more accurately reproduce the performance of receivers in real networks than high-bandwidth oscilloscopes. The input bandwidth of serdes receivers is generally close to the Nyquist frequency of the data, which is much smaller than that of oscilloscopes. The eye openings of oscilloscope eye diagrams appear larger than measured by BERT EDs because, like serdes receivers, EDs are band limited. The result is that eye diagrams analyzed by EDs more closely resemble those in the test receiver's clock recovery, equalization, and logic decoding circuits.
Three EDs are recommended to identify PAM4 symbols and measure the signal. Since most first-generation PAM4 receivers will use synchronized samplers, the specified minimum BER performance usually assumes that the time-delay positions of all three EDs are synchronized. The center of the eye is usually defined by the center of the middle eye diagram.
The PAM4 BER measurement is a bit involved. Thankfully, it can be completely automated. Here is an example.
The error detector that samples the lowest of the three eyes is ED1 with voltage sampling point VSP1. Similarly, the middle error detector, ED2, samples at VSP2 and ED3 samples at VSP3, as in Figure 4. Separate EDs can monitor bits from either the LSB or MSB patterns. To measure BER on the PAM4 signal, one of the three possible symbols needs to be masked to prevent the third ED from counting spurious bits.
Engineers can compose symbols by adding the digital values of the LSB and MSB. The LSB is the first digit in the binary pair, either 0 or 1 in both binary and decimal, while the MSB is the second digit, either 00 or 10 corresponding to 0 or 2 in decimal. These values for the LSB and MSB are shown in the first row of the timing chart shown in Figure 5.
The symbols resulting from the sum of the LSB and MSB are the second row of the chart. The three EDs determine whether a symbol is above or below their voltage sampling point threshold. By masking the symbol observed by ED3, and comparing the bits identified by ED1 and ED2 to the transmitted LSB and MSB, the number of bit errors is recorded.
The second PAM4 symbol is S0. No ED should latch but to match the LSB and MSB to the appropriate error detector, ED1 must be masked. Similarly, the third PAM4 symbol is S3. All three EDs should latch, but to match the MSB and LSB to the correct ED, ED3 must be masked so that ED1 monitors the LSB and ED2 monitors the MSB.
In Figure 5, the masked symbols have white backgrounds and the counted symbols have blue or yellow backgrounds corresponding to the transmitted test pattern. The result is a three ED configuration that automatically masks the appropriate ED for each symbol and faithfully measures the BER, not the SER, of PAM4 signals.
PAM4 introduces many new challenges. By starting with a pristine test signal and adding well understood signal impairments, engineers can be certain that components will be compliant interoperable network elements. Additionally, 4-channel EDs with excellent sensitivity and fine phase resolution should serve as golden reference receivers to most accurately analyze the intricacies of PAM4 signals.