PAM4 receivers are complex, as they have AC coupled front ends, clock recovery circuits, equalizers and three integrated voltage slicers in one unit. To diagnose hardware problems, distinct stresses are used to challenge each component. For compliance testing, all the components must be stressed simultaneously.
It's imperative for both diagnostic and compliance testing to start with pristine, instrument-quality, low SNR signals. With 12 distinct rise and fall times, it's also crucial that the unstressed PAM4 test signal have wide open eye diagrams that require sharp symbol transitions. To make accurate tests, PPGs should have rise/fall times faster than 12 ps and apply adjustable levels of every stress type required for compliance measurements of every major technology standard.
Some PAM4 receivers can count their own errors either through their FEC coding block, which is capable of counting considerably more errors than it can correct, or through internal frame loss rate (FLR) detection. Most PAM4 standards specify BER < 1E-6 or 5E-5, independent of FEC, or FLR < 6.2E-10 for 512 bit frames, including FEC. These requirements assure post-FEC performance of BER < 1E-15.
In moving from two-symbol NRZ to four-symbol PAM4 a factor of two in bandwidth is achieved. The trade-off, however is increased complexity and signal-to-noise ratio (SNR). With four levels, PAM4 signals have three distinct but not independent eye diagrams. The voltage swing between adjacent levels is no more than one third the swing between NRZ levels. This lowers the SNR by at least 9 dB from what is typical with NRZ signals. For this reason, a BERT ED should serve as a golden reference receiver and signal quality analyzer when analyzing PAM4 signals.
BERT EDs must have excellent sensitivity to make accurate measurements of the high SNR, low voltage-swing PAM4 eye diagrams. ED sensitivity is the smallest voltage swing for which the ED can distinguish symbol levels. For PAM4 measurements, ED sensitivity should be typically 10 mV.
BERT EDs more accurately reproduce the performance of receivers in real networks than high-bandwidth oscilloscopes. The input bandwidth of serdes receivers is generally close to the Nyquist frequency of the data, which is much smaller than that of oscilloscopes. The eye openings of oscilloscope eye diagrams appear larger than measured by BERT EDs because, like serdes receivers, EDs are band limited. The result is that eye diagrams analyzed by EDs more closely resemble those in the test receiver's clock recovery, equalization, and logic decoding circuits.
Three EDs are recommended to identify PAM4 symbols and measure the signal. Since most first-generation PAM4 receivers will use synchronized samplers, the specified minimum BER performance usually assumes that the time-delay positions of all three EDs are synchronized. The center of the eye is usually defined by the center of the middle eye diagram.
The PAM4 BER measurement is a bit involved. Thankfully, it can be completely automated. Here is an example.
The error detector that samples the lowest of the three eyes is ED1 with voltage sampling point VSP1. Similarly, the middle error detector, ED2, samples at VSP2 and ED3 samples at VSP3, as in Figure 4. Separate EDs can monitor bits from either the LSB or MSB patterns. To measure BER on the PAM4 signal, one of the three possible symbols needs to be masked to prevent the third ED from counting spurious bits.
Engineers can compose symbols by adding the digital values of the LSB and MSB. The LSB is the first digit in the binary pair, either 0 or 1 in both binary and decimal, while the MSB is the second digit, either 00 or 10 corresponding to 0 or 2 in decimal. These values for the LSB and MSB are shown in the first row of the timing chart shown in Figure 5.
The symbols resulting from the sum of the LSB and MSB are the second row of the chart. The three EDs determine whether a symbol is above or below their voltage sampling point threshold. By masking the symbol observed by ED3, and comparing the bits identified by ED1 and ED2 to the transmitted LSB and MSB, the number of bit errors is recorded.
The second PAM4 symbol is S0. No ED should latch but to match the LSB and MSB to the appropriate error detector, ED1 must be masked. Similarly, the third PAM4 symbol is S3. All three EDs should latch, but to match the MSB and LSB to the correct ED, ED3 must be masked so that ED1 monitors the LSB and ED2 monitors the MSB.
In Figure 5, the masked symbols have white backgrounds and the counted symbols have blue or yellow backgrounds corresponding to the transmitted test pattern. The result is a three ED configuration that automatically masks the appropriate ED for each symbol and faithfully measures the BER, not the SER, of PAM4 signals.
PAM4 introduces many new challenges. By starting with a pristine test signal and adding well understood signal impairments, engineers can be certain that components will be compliant interoperable network elements. Additionally, 4-channel EDs with excellent sensitivity and fine phase resolution should serve as golden reference receivers to most accurately analyze the intricacies of PAM4 signals.