Digital signal fanout is a very common requirement in testing, experimentation, and systems integration. Unlike radio frequency signals, high-speed digital signals cannot be simply split or "teed" off to multiple destinations. Even with a matched-impedance splitter, the resulting amplitude loss would render most clock and logic signals incompatible with the receiver. To preserve logic level compatibility, digital signals must be actively buffered when they are fanned out. Several factors must be controlled when building a fanout buffer for lab use, and each becomes more difficult at higher data rates and with longer cable lengths:

  • If the transmission distance is a "long line," (i.e. if the propagation delay tprop to the receiver is > 20-25% of the rise-time tr of the signal) a controlled-impedance environment is mandatory. When driving a long line, either the driver must have a back termination, or else the line must be terminated at the receiving end.
  • When driving very long cables (in excess of 10' - 20'), series resistance and the "skin effect" of the cable will degrade the signal amplitude, requiring the output driver to have significant headroom to trigger the receiver reliably.
  • Once a suitable circuit has been designed, carefully integrating all the necessary components for daily laboratory use involves more than just bread-boarding. It requires a PC board with controlled impedance I/O lines, an enclosure, I/O connectors, power supplies, and components for biasing of the I/O circuits, etc.

When considering common tasks in the digital electronics domain, such as clock distribution to multiple receivers, data fanout to multiple receivers, and synchronous triggering of multiple receivers, semiconductor manufacturers offer numerous devices for signal fanout at the PCB level. For example, one device provides 1:6 TTL fanout up to 100 MHz, and another provides 1:2 fanout for ECL up to 2.5 GHz. These devices offer solutions to the engineer working within the relatively small confines of a circuit board.

In order to accomplish the above tasks at the instrumentation and interconnect level, a series of self-contained, fanout buffer modules (for TTL and ECL) have been developed to give engineers the ability to fanout TTL signals up to 100 MHz and NECL/PECL/LVPECL signals up to 3 GHz. The output driver circuitry is designed to drive 50Ω loads while preserving timing fidelity and logic-level amplitudes. With proper load termination, TTL models can drive up to 100 feet of cable, and differential ECL models can drive up to 200 feet of cable. TTL and PECL models also have back-termination for driving un-terminated loads.

Practical considerations, such as efficiency and cost-effectiveness in the lab, should be factored into the build-vs.-buy equation. Although conceptually simple, a project like this can consume hours or days of troubleshooting time. Furthermore, projects like these are not highly repeatable, unless a PC board is laid out, which again involves additional time and cost.

This work was done by David Kan and Steven Kan for Pulse Research Lab (PRL). For more information on using PRL's Fanout Buffer Modules, contact Pulse Research Lab, 1234 Francisco Street, Torrance, CA 90502; Tel: (310) 515-5330; Fax: (310) 515-0068;