A new design for a complementary metal oxide/semiconductor (CMOS) snapshot imaging device of the photodiode-based, active-pixel-sensor (APS) type calls for features to prevent photogenerated electric charges collected during a given frame period from leaking into in-pixel capacitors that store charges collected during the preceding frame period, pending completion of readout from that period. The proposed design would also utilize the electronic-shuttering capability of an APS to provide for programmable exposure time, down to (≈10μs) a small fraction of the frame period, to enable faithful recording of images of rapidly moving objects. Finally, the design would make it possible to obtain quantum efficiency higher and readout noise lower than those of a typical prior CMOS APS imaging device.
The circuit in each pixel of a typical CMOS snapshot imaging device (see Figure 1) includes a storage capacitor (Cp) that serves as both a frame buffer memory (as described above) and a sensing node. The photodiode in this circuit converts incident photons to electrons during an exposure time that is defined as the time during which transistor switch RST-D is kept open. The possibility of controlling this time by controlling the duration of a pulse that controls RST-D (in other words, electronic shuttering) is what makes it possible to set the exposure time at any desired fraction of the frame period.
During the exposure, photoelectrons are stored temporarily in the photodiode capacitance (Cd). After the exposure, Cpis reset (that is, purged of the charge from the preceding frame period) by momentary closing of transistor switch RST-C. During this reset, part of the charge accumulated in Cd during the just-completed exposure is transferred to Cp by momentarily closing the transistor switch labeled "Share." Once this transfer of charge has been completed, the photodiode is available to begin a new frame exposure, and the charge newly transferred to Cp is held there until it is read out at its assigned time in a row-by-row readout sequence that is completed before the beginning of the next frame period.
The design and operation of a typical prior CMOS snapshot imager as described thus far raise three main concerns that are addressed by the proposed design:
- The leakage mentioned above is an unwanted lateral diffusion of charge from Cd to Cp during exposure. This leakage is deleterious because it gives rise to image smear and, in the case of movement in the image, it introduces motion-related artifacts.
- The transistor switches and the storage capacitor in each pixel reduce the fill factor (the fraction of pixel area devoted to photodetection), thereby reducing quantum efficiency.
- Readout noise includes significant contributions from resetting of Cp, resetting of Cd, and sharing of charge between Cp and Cd.
In the proposed design (see Figure 2), the pixel circuit elements would be configured to create an electric field that would prevent the diffusion of photoelectrons into Cp. The design would be implemented in a twin-well process with a lightly doped epitaxial layer to ensure excellent collection of photoelectrons. The n well would act as a photodiode, and the storage capacitance would be implemented in the p well as a diffusion or a gate capacitance. The transfer gate would be driven by the "Share" transistor switch as in Figure 1. The storage node would be shielded by metal to maintain the integrity of stored photocharges. The storage node in the p well would be held at ground potential. Hence, electrons generated in the p epitaxial layer or the n well (which would be biased above ground) would be prevented, by the resulting potential barrier, from reaching the storage node. Furthermore, the n++-doped subregion in the storage-node region would be reverse-biased, so that no holes would reach it. Holes would be drained at a p++ contact (not shown in the figure) in the p well. Thus, the storage node would be protected against any coupling from the photodiode, enabling smearless imaging.
A major characteristic of this configuration is that the storage capacitance per unit area would be orders of magnitude greater than that in a corresponding prior design, so that it would be possible to make Cpoccupy a much smaller area; hence, there would be plenty of margin to choose whatever value of Cp is needed to minimize readout noise, without risk of significantly decreasing the fill factor and thus the quantum efficiency along with it. (The optimum choice of Cp to minimize readout noise turns out to lie between 0.7× and 1× Cd.)
This work was done by Bedabrata Pain of Caltech for NASA's Jet Propulsion Laboratory.
In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to
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This Brief includes a Technical Support Package (TSP).
Leakage-Preventing Design of Snapshot Photodiode CMOS Imager
(reference NPO21044) is currently available for download from the TSP library.
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