Two improved schemes for the design and operation of photodiode-based CMOS (complementary metal oxide/ semiconductor) active-pixel sensors (APSs) afford zero image lag, low noise, and high linearity of response even under low illumination. Figure 1 schematically depicts the circuitry for one pixel according to a typical older scheme. In soft reset, the sensing node does not charge up to the power-supply potential (VDD), and depends strongly on the potential at the beginning of the reset. In hard reset, the sensing node charges up to a known potential, usually VDD.

For reasons that are complex and must therefore be omitted from this article for the sake of brevity, typical older soft- and hard-reset schemes entail disadvantages and advantages as follows:

  • Soft reset advantageously results in low-noise output and a high power-supply rejection ratio (PSRR). However, disadvantageously, soft reset results in image lag of as much as 70 percent of the mean signal in the previous frame, and a markedly nonlinear response under low illumination.
  • Hard reset advantageously eliminates image lag but disadvantageously results in increased read noise, dark current, and reduced power-supply ratio.

Under the improved schemes, the disadvantages are eliminated by resetting pixels first by hard reset and then by soft reset. Hard reset erases the memory from the previous frame, eliminating image lag and nonlinearity, while soft reset allows operation with low-read noise. Thus, low noise, zero image lag, and high linearity are achieved simultaneously.

Figure 1. A Typical Prior CMOS APS Circuit is designed and operated according to a soft- or a hard-reset scheme. Both schemes entail advantages and disadvantages.

Figure 2 illustrates the pixel circuits that are used for implementation of the two new schemes, which are characterized by the terms "flushed photodiode" and "hard-to-soft (HTS) reset photodiode," respectively. In the flushed-photodiode APS, the pixel circuit contains an additional line (denoted "HTSffÄBlack") for a row-decoded signal that controls the potential at the drain of the reset MOSFET (metal oxide/semiconductor field-effect transistor). Pulsing HTS reduces the drain potential, allowing the pixel to be reset in hard reset mode. In the HTS APS, no change in the pixel design is necessary. In this scheme, VDDis routed to each column through an n- and a p-channel MOSFET. The gate of the p-channel MOSFET is connected to a line (denoted "HTS") that carries a column-decoded signal. Pulsing HTS momentarily high during the reset phase causes the source of the reset MOSFET to reduce below VDD, causing the pixel to go into hard reset. The hard-reset level is determined by the size of the n-channel MOSFET, and is set to approximately VDD/2. In both schemes, soft reset of the pixel following the hard reset is achieved once the HTS pulse goes low.

This work was done by Bedabrata Pain, Guang Yang, Thomas Cunningham, and Bruce Hancock of Caltech for NASA's Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Technology Reporting Office
JPL
Mail Stop 122-116
4800 Oak Grove Drive
Pasadena, CA 91109
(818) 354-2240

Refer to NPO-20716

Photonics Tech Briefs Magazine

This article first appeared in the November, 2000 issue of Photonics Tech Briefs Magazine.

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