Fiber-optic transceivers (FOTs) that can handle digital signals at any bit rate from 10 to 300 MHz have been developed. These variable-rate FOTs offer considerable advantages over fixed-rate FOTs that have been used until now. A fixed-rate FOT contains clock- and data-signal-recovery circuits tuned to the data rate. In a system in which data streams are transmitted at different rates, the data rates must be specified in advance, and a separate fixed-rate FOT must be designed, constructed, and installed for each rate. Thus the cost of acquiring, maintaining, and operating fixed-rate FOTs for a multiple-rate system can be high, and under some circumstances, advance notice of data rates could compromise security. Obviously, costs can be reduced and security enhanced by use of variable-rate FOTs capable of operating over the full range of data rates.

The Clock-Signal-Recovery Circuit Is the Critical Unit that implements the VBS process and thereby enables the fiber-optic transceiver to handle data at any rate over a wide range.

Each transceiver includes a transmitter and a receiver module (see figure). The primary function of the transmitter module is performed in an encoder, which inserts one overhead bit for every eight data bits in a non-return-to-zero (NRZ) serial data stream. The overhead bits are used to prevent lockup in a scrambler, and they remove all constraints on the input data pattern. The rate of the transmitted serial data stream is thus 9/8¥ the input data rate.

In the receiver module, an optical receiver converts the incoming light signal to a bit-serial electrical signal. This electrical signal is fed to a clock-signal-recovery circuit, which implements a method, called "variable bit synchronization" (VBS), for recovering a clock signal characterized by a rate that could vary over a wide range. In VBS, the synchronous clock signal is reconstructed from the composite (clock + data) bit-serial electrical signal, then the data signal is regenerated with reclocking. The VBS process is what makes it possible to transmit NRZ data and clock signals over a communication channel and to recover these signals within a wide frequency range.

The lower part of the figure illustrates the clock-signal-recovery circuit and the VBS process in more detail. A bit-rate estimator provides an estimate of the incoming data rate. The estimate is used by a direct digital synthesizer (DDS) to acquire the clock frequency and achieve synchronization as follows: The output of the DDS is processed through a phase-lock loop that multiplies frequency by a factor of 128/N (where N is an integer). A controller sets up the DDS and PLL to generate a signal with a frequency within 3 percent of the actual clock frequency. The DDS is then swept into exact frequency and phase lock by a vernier sweep circuit. Typically, the clock-signal-acquisition process takes about 2 seconds.

The clock and data outputs of the clock-signal-recovery circuit are fed to a descrambler. The output of the descrambler is fed to a decoder, which strips off and frame-locks to the overhead bits and reconstructs the original NRZ data stream. The decoder also performs an 8/9 frequency multiplication on the reconstructed clock signal to recover the clock signal of the original data stream. The overhead bits and the frame-synchronization process that involves the overhead bits provide a benefit of continuous in-service error detection.

One particularly attractive feature of the variable-rate FOT is its ability to function without intervention by a technician once it has been installed. In operation, the receiver reconstructs the original clock and data signals at their original rates, with a bit-error rate of 10-12 or less.

This work was done by Chi Le of Goddard Space Flight Center, Paul Casper of Broadband Communications Products, and Jim Shaughnessy of Computer Sciences Corp. For further information, access the Technical Support Package (TSP) free on-line at under the category. GSC-13782