Parallel ultra-low-noise hybrid detectors (PHUDs) are developmental image-detector devices for use in low-power, scientific-grade video cameras. The hybrid nature of a PHUD lies in the incorporation of both charge-coupled-device (CCD) image-detection circuitry and complementary metal oxide/semiconductor (CMOS) parallel readout circuitry. PHUDs promise to revolutionize optical spectrometers and related instruments by providing low-noise, single-photon detection capabilities at conveniently high video data rates.
Until now, subelectron-noise, single-photon-detection capabilities have been achieved by multisampling, nondestructive readout from CCDs. The major disadvantage of this approach is slowness, because of a need to sample each data packet 10 to 100 times in serial fashion; readout rates have been of the order of 5 ×104 pixels per second, resulting in readout times of tens of seconds per frame for typical images of 800 × 800 pixels. In principle, multisampling could be speeded by performing it in parallel instead of serial fashion, but attempts to implement parallel sampling have resulted in excessive power consumption (>1 W per CCD) and consequent excessive heating that degrades device performance.
In contrast, PHUDs are designed to achieve low noise (<1 electron root mean square), and readout rates of the order of 106 pixels per second while consuming less than 50 mW per device. The key design concept of PHUDs is exploitation of the best features of both CCDs and of CMOS imaging devices:
- CCD Features - High quantum efficiency, broad spectral response, low readout noise, high resolution, and large format.
- CMOS Features - Low power consumption, capability for on-chip implementation of such additional functions as digitization and multiplexing, and compatibility with external CMOS circuitry.
The design of a PHUD involves not only hybridization of CCD and CMOS components but also departures from conventional designs of these components. The conventional high-speed serial register is removed from the CCD, a charge-conversion structure is incorporated at the output end of each column in the CCD, and a high-speed CMOS multiplexer for output of voltage-domain signals is added. The signal charge is sensed by a floating polysilicon gate or other suitable nondestructive sensing node located within the CCD at the output end of each column. Charge conversion occurs simultaneously for all columns of pixels. The charge packet in each pixel in a given row and column is measured N>1 times on the sensing node of the column, and each measurement is stored in the CMOS chip by means of an averaging circuit; the resulting readout noise is approximately N-1/2times what it would otherwise be. Because this multiple sampling occurs simultaneously for all pixels along a row, the overall frame rate is not appreciably diminished.
Column-to-column variations in signal offsets and gains in a PHUD can readily be corrected in the course of routine digital processing of readouts. Calibration data for use in computing the corrections are averages and variances of readouts from uniform images.
This work was done by Mark V. Wadsworth of Caltech for NASA's Jet Propulsion Laboratory. NPO-20576
This Brief includes a Technical Support Package (TSP).
High-speed image detectors with subelectron noise floors
(reference NPO20576) is currently available for download from the TSP library.
Don't have an account? Sign up here.