Thermal issues are dominating today’s electronic product design landscape as never before. It is easy to see this in Intel’s move to a multi-core architecture as a methodology to manage their thermal problems. Of course, less than optimal solutions lead to less than optimal results. Thermoelectric devices (TECs) have been used in the optoelectronics industry for thermal management, but have not found wide-spread acceptance in electronic product design. Thermal management solutions implemented with these active devices, however, offer a broad potential for implementation including the following:

Figure 1. Thermal and electrical bumps integrated on a single substrate.

General cooling: TECs can be evenly distributed across the surface of a chip to provide an evenly distributed cooling effect or they can be placed to locally cool a hot spot. In the former case, these devices are typically placed in the heat spreader or heat sink to provide cooling in the form of an active heat sink or heat spreader.

Hotspot cooling: In microprocessors, graphics processors, and other high-end chips, hotspots can occur as power densities vary significantly across a chip. These hotspots can severely limit the performance of the devices. Today this problem has been placed on the back burner through the use of multi-core architecture but it is inevitable that in a few years it will come back.

Precision temperature control: Since thermoelectric devices can be used to either cool or heat the chip, depending on the direction of the current flow, they can be used to provide precision control of temperature for chips that must operate within specific temperature ranges irrespective of ambient conditions. This is a common problem for many opto-electronic components.

Power generation: In addition to chip cooling, thermally active devices can also be applied to high heat-flux interconnects to provide a constant, steady source of power for energy scavenging applications. Such a source of power, typically in the mW range, can trickle-charge batteries for wireless sensor networks and other battery-operated systems.

Integrating the Thermoelectric Function

Acceptance of discrete thermally active devices has not found the wide-spread acceptance in the electronic product world that it has in the opto-electronic product world. In large measure this is due to the dissimilar manufacturing processes used for the two types of products.

If a solution is to be found that brings active thermal management into the mainstream for electronic product design, it needs to be integrated directly into the existing packaging infrastructure. The integration of a thermally active material into a flip chip solder bump, or more specifically into a Copper Pillar Bump (CPB) to form a thermal bump, offers just such a solution.

The Thermal Copper Pillar Bump

The Thermal Copper Pillar Bump, also known as the thermal bump or TCPB, is a thermoelectric device made from thin-film thermoelectric material embedded in flip chip interconnects (in particular Copper Pillar Bumps) for use in electronics and optoelectronic packaging, including flip chip packaging of CPU and GPU integrated circuits (chips), laser diodes, and semi-conductor optical amplifiers (SOA). Unlike conventional solder bumps that provide an electrical path and a mechanical structure for connection to the package, thermal bumps act as solid-state heat pumps and add thermal management functionality on the surface of a chip or other electrical component. The diameter of a thermal bump is 238 μm (microns) and they are 60 μm high.

Figure 2. 3D thermal management.

For each bump, cooling occurs when a current passes through the bump. The thermal bump pulls heat from one side of the TEC and transfers it to the other as current is passed through the material. This is known as the Peltier effect. The direction of heating and cooling is determined by the direction of current flow and the sign of the majority electrical carrier. Thermoelectric power generation (TEG), on the other hand, occurs when the thermal bump is subjected to a temperature gradient (i.e., the top is hotter than the bottom). In this instance, the device generates current, converting heat into electrical power. This is termed the Seebeck effect.

The thermal bump was developed as a method for integrating thermal management capabilities at the chip level in the same manner that transistors, resistors, and capacitors are integrated in conventional circuit designs today. Nextreme chose the copper pillar bump as an integration strategy due to its current acceptance by Intel, Amkor, and other industry leaders as the method for connecting microprocessors and other advanced electronics devices to various surfaces packaging. The thermal bump can be integrated as a part of the standard flip-chip process (Figure 1) or integrated as discrete devices.

Cooling of electronic devices is most efficient when it occurs closest to the source of the heat generation because the efficiency is inversely proportional to the temperature. Use of the thermal bump does not displace system level cooling, which is still needed to move heat out of the system; rather it introduces a fundamentally new methodology for achieving temperature uniformity at the chip and board level. In this manner, overall thermal management of the system becomes more efficient. In addition, as system-level solutions scale with the size of the system (bigger fans for bigger systems, etc.), the thermal bump can scale at the chip level by using more thermal bumps in the overall design.

Example Application: 3D Thermal Management

As an example of integrating thermal management capabilities at the chip level, consider thermal management of a 3D chip stack structure using thermal bumps. Figure 2 illustrates the 3D thermal management concept by broadening what had been back-side cooling to include active or front-side heat removal along with lateral heat removal.

Back-Side Cooling: Back-side cooling can be enhanced by the introduction of thermal bumps either into the heat sink to form an active heat sink or into the heat spreader. This is behind the first level or TIM one (thermal interface material).

Lateral Cooling: For a 3D chip stack, lateral heat removal can be combined with an interposer through which the heat can be removed. Here the thermo-electric material is underneath the substrate and the heat is pulled from the center segment to the side. Therefore the center of the platform will be cool and the sides will be hotter. In this embodiment, the heat is dissipated to the walls.

Active-Side Cooling: The last concept is active-side cooling. Here we show the active side of the CPU interspersed with conventional copper pillar bumps and thermal bumps, strategically placed near the hot spots. For hot spot cooling, you don’t have to cool an area of 1mm by 1mm; only an area of 100mm by 100mm may be sufficient.


A new opportunity exists to begin next-generation electronic product design by including chip and module-level thermal management directly into the packaging process. In the same manner that silicon shrinks have made electronic products ubiquitous in our daily lives, so will shrinking the physical scale of thermal management materials. Integrating thermoelectric materials into the interconnect structure for advanced packing processes, instead of as device add-ons, opens the door to chip-level thermal management.

This article was written by Dr. Paul Magill, VP Marketing & Business Development, Nextreme Thermal Solutions (Durham, NC). For more information, contact Dr. Magill at This email address is being protected from spambots. You need JavaScript enabled to view it., or visit

Photonics Tech Briefs Magazine

This article first appeared in the July, 2008 issue of Photonics Tech Briefs Magazine.

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