For the last 20 years we have connected our monitors to our computer systems having the confidence that upon turn-on, we could surf or create with never a consideration of whether the display would operate satisfactorily. VGA (Video Graphics Adaptor) technology enabled us to do that with CRTs as well as with flat panel displays. Now, however, the viewing benchmarks are being reset, as are system design considerations. There’s a new interface on the horizon called DisplayPort!

DisplayPort is being administered under the auspices of VESA (Video Electronics Standards Association) and is directly targeted for digital video content to PC monitors. The interface was released in May of 2006 and its second revision was released earlier this year. It has big names behind it such as Dell, HP, and Intel, and the pace of the rollout, as well as the commitment from IC vendors, herald DisplayPort’s potential success as a replacement for VGA. With respect to the “unconsciousness interoperability” that VGA provided, you can rest assured that VESA is working hard to maintain that reality with DisplayPort.

You might remember that DVI (Digital Visual Interface) offered similar promise a number of years ago, but for various reasons never really took off. DVI even implemented a viable transition strategy with its DVI-I connector that included VGA capability directly with its digital interface. The connector, three times the cross sectional area of the DisplayPort connector, was uninspiring and DVI quite simply languished. Size not withstanding, what are the other consumer recognizable benefits of DisplayPort? Aside from the push-in connector with latching mechanism there really isn’t much else one can directly see. There is, however, a number of points when you consider what is enabled by the DisplayPort technology.

DisplayPort Interface

The DisplayPort interface is integrally composed of 4 data lanes, 1 auxiliary channel, and a hot plug detect (HPD). The data lanes (Main Link) are unidirectional from the source to the sink, 100 ohm differential, and can operate at either 1.62 or 2.7 Gbs. The auxiliary channel (AUX) is a lower rate (1Mbs) communication path between a DisplayPort source and a DisplayPort sink where the source is the master. The receiver can initiate service from the source by asserting the HPD line. The specification defines four different Main Link levels (400, 600, 800 and 1200 mVolts pk-pk) as well as four possible pre-emphasis settings for these lanes (0, 3.5, 6, and 9.5 dB). Further, to complete the ultimate configurability of the interface, the specification allows for one, two, or four lane operation. The interface supports not only box-to-box but an embedded implementation model as well.

Benefits of DisplayPort

Consider, a source/sink connection that is marginal or worse. What system today could handle the situation without user interaction? The configurability of the main link and the link communication path (Aux channel) makes it clear that DisplayPort is a very dynamic interface that will adapt as necessary to optimize the link. For the user this usually means to choose the highest resolution possible, and thus best viewing quality possible for his/her system. For the system designer, it may mean the fewest number of wires from source to sink, or the least amount of power, the least expensive cable, or the longest cable. For our example of a marginal setup, the DisplayPort sink could assert the HPD line and, when queried, could recommend to the DisplayPort source a higher transmitted voltage, more preemphasis, or lower data rate.

For PC manufacturers, DisplayPort enables a concept called “Direct Drive” which merely means that the display module can be directly connected to the cable input without having to go through a TMDS (Transition Minimized Differential Signaling. Used in HDMI and DVI systems.) receiver or a scalar device. In addition, DisplayPort can be implemented on the latest IC processes (65nm) because it allows for a lower bias voltage. The implication here is that motherboard pin count, IC count, and power requirements are reduced.

Testing and Validation

VESA is anticipating a comprehensive testing and compliance program for DisplayPort.

This program includes product certification at independent third party test houses such as Allion, NTS, Contech Research, and ETC as well as plugfest events which enable a verification-by-connection approach. The compliance program is administered by VTM, which oversees similar activities for PCI-Express as well as USB. As with many modern digital interfaces, testing DisplayPort is separated into two areas: protocol/link verification and physical layer testing. Testing regimens for both are captured in CTS (compliance test specification) documents for the standard that are available on the VESA website for members.

Link Layer/Protocol Testing: Link Layer testing verifies link initiation, training, and maintenance while protocol testing verifies packet construction and content. Clearly, with the dynamic approach DisplayPort enables, link layer validation is extensive. Testing the link layer requires devices called Reference Sink, and Reference Source, which effectively are controllable DisplayPort devices that have readable and settable registers and can engage the complementary DisplayPort device as in normal operation.

Physical Layer Testing: physical layer testing is separated into sink, source and cable testing. All of these have fixture requirements to get to and from the DisplayPort device under test, so a test point access fixture is a key test solution element. To test a DisplayPort sink, a pattern generator with precise level and jitter control is required as is a means to read a bit error counter register in the sink device. [This function could be accomplished by a reference source]. The sink test is a jitter tolerance test where a PRBS 7 pattern is continuously transmitted and the sink evaluates its recovery, incrementing the counter on every error. Cable test is the realm of time domain reflectometers(TDR) and vector network analyzers and covers parameters such as crosstalk, impedance, return loss and gain. The source test regimen is much more extensive and covers eye testing, total jitter evaluation, pre-emphasis and level accuracy as well as spread spectrum clocking tests (SSC is optional in the standard).

DisplayPort Test Equipment

The physical layer measurement equipment required for DisplayPort is common to many of the other digital interface standards. To perform the jitter tolerance test for sinks for example, the Agilent N4903A J-BERT can be used. It provides an intuitive user interface to set the test voltage levels, the amount and type of jitter desired and to establish the link training sequence. The training sequence consists of an alternating pattern for frequency lock of the receiver clock, then a K28.5 pattern is needed for symbol lock, and a third repetitive pattern is needed for error counting. The N4903A interface allows an arbitrary sequencing of these patterns in a phase continuous manner to ensure synchronization of the receiver throughout the initialization (signal locking) and error counting phases.

Another challenge facing designers is the impedance matching from the DisplayPort chip, through the PC board to the DisplayPort connector. Considering the pressure for low cost materials such as FR4 printed circuit boards, impedance control will be an issue. To evaluate impedance, a time domain reflectometer (TDR) or a vector network analyzer (VNA) must be used. The Agilent 86100C is ideal for this evaluation because not only can it locate impedance discontinuities, it can measure s-parameters as well as jitter on live traffic. Finally, the source testing requirements are extensive as the CTS calls out 17 different tests. These can all be done on a realtime oscilloscope.

Summary

DisplayPort is poised to hit the industry with an extremely fast ramp. It is an interface that optimizes usability, robustness, and application, while minimizing cost and power. It also has plenty of headroom for future resolution increases, making it a likely successor to the VGA legacy of interoperability.

This article was written by Brian Fetz, Serial Applications Product Manager for High Performance Oscilloscopes, Agilent Technologies (Spokane, WA). For more information, contact Mr. Fetz at This email address is being protected from spambots. You need JavaScript enabled to view it. or visit http://info.hotims.com/10981-201.


Photonics Tech Briefs Magazine

This article first appeared in the November, 2007 issue of Photonics Tech Briefs Magazine.

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