Fuelled by an increasing demand for bandwidth combined with a continued drive towards cost and size reduction, larger scale photonics integrated circuits are now clearly breaking through. For example, fiber optics networks are rapidly embracing 40Gbps and 100Gbps data rates, where the transmitters and receivers often include photonic integrated circuits. And the cost and size reduction in 10Gbps transceivers has driven several companies to successfully leverage photonic chips. The growing FTTH (fiber to the home) market is driving demand for integrated photonic splitters as well as monolithically integrated BiDi transceivers. And there are exciting applications in fiber sensing and bioscience that are now benefiting from optical chips as well.
At the same time, many photonics players have recognized that it is unaffordable to run their own fab and thus rely on foundries to manufacture these photonic integrated circuits. However the maturing field of integrated photonics needs better tools to streamline the design, packaging and fabrication of photonic chips. One approach is to borrow these tools from the integrated electronics industry that has successfully used foundries for a long time. By using design automation tools, photonic chip designs can become first-time-right. This, in turn, can lead to large cost savings through increased yields, by reducing the number of wafer iterations and by participating in Multi Project Wafer (MPW) runs.
Photonics Design Automation
In the electronics industry, the use of “Electronics Design Automation” (EDA) is widespread. A foundry offers an extensive set of building blocks (BBs), which a designer can use to create a complex device. These building blocks and their combination are guaranteed to work as expected if the given design rules are respected. Software supports each step in the design process, from physical analysis to layout and design rule checks before the final design is sent to the foundry. Advanced simulation tools can be directly linked to this EDA environment and greatly assist the designer in his work.
Within the context of several European programs, such as Paradigm, Helios and Memphis, a large number of European companies and institutions have worked together to set up a Photonics Design Automation (PDA) tool-set with this capability. Just like in EDA, photonic foundries define a number of building blocks in software tools ranging from physical and circuit simulators to mask layout.
Since the building blocks of one foundry are often very similar to those of other foundries, many designs can be easily ported from one foundry to another. Such a transfer can be done with hardly any changes to the chip performance, but with significant changes to the mask layout in order to accommodate different processes at the other foundry.
Integrated Product Creation Process
Underpinning the generic manufacturing concept is the fact that product design, process design, and high-yield manufacturing are intimately linked and cannot be separated. For this reason, the key information flow between the different stages of product and process development needs to be made available to all stakeholders through the use of software. When system engineers, design engineers, and process engineers work seamlessly together to design both the product as well as the required fabrication processes, this is known as the integrated Product Creation Process (iPCP) as shown in Figure 2.
This iPCP has been implemented in several European projects by developing foundry specific design kits. These kits allow users to benefit from mature technologies, while avoiding recurring costs by streamlining the discussions between the designers and the engineers at the foundry.
Using Photonic Design Automation Tools
A designer of a Photonic Integrated Circuit (PIC) starts by modeling any components that are not part of a foundry's standard building blocks through the use of a propagation simulator. Once those building blocks are defined, the designer can combine them together with the foundry's standard building blocks and analyze the performance of a complete chip using a circuit simulator. It is through the use of design kits that the foundry's standard building blocks become available to the PIC designer. In the circuit simulator, the wavelength dependent scattering matrix of each building block is used to efficiently calculate the overall behavior of the chip. The designer can thus quickly optimize a photonic integrated circuit for best performance, highest yield, lowest cost, and robustness against manufacturing tolerances.
One particular advantage of working with Photonics Design Automation is that a foundry can make available unique building blocks that are covered by patents or trade secrets. The unique building block is shown as a bounding box that hides what is inside the box, but does detail the location of input and output waveguides as well as the functionality of the building block through a wavelength dependent scattering matrix.
Once a satisfactory design has been created with a specific foundry and package in mind, it can be transferred via the PDA framework to MaskEngineer or other mask layout software. The mask layout can then be further optimized, after which the PIC design is translated into mask files. During this process, automatic post processing takes place that obeys design rules set by the foundry. For example, a waveguide may have to be wider on the mask than in the original design in order to compensate for a known amount of underetch. Or the definition of a waveguide may involve a local mask inversion if the waveguide is created using lift-off rather than through etching. In addition, the PDA framework will perform foundry specific design rule checks (DRC) at the logical and mask levels. The design can, for example, be checked for the minimum allowable bending radius. Or a check is performed to ensure that metalization and waveguide layers are neither overlapping nor closer than a minimum distance.
The designer will subsequently send the mask files to the foundry, which performs final processing. If a protected building block is used, the foundry will replace the bounding box with the actual design layout. The foundry may also add process control modules. And when the PIC design is part of a Multi Project Wafer (MPW) run, the foundry will collect the mask files from all participating users and place them in individual reticles. When the mask set is ready, the wafers can then be processed by the foundry.
Multi Project Wafer Runs
While Photonic Design Automation delivers indispensable tools to streamline chip runs for foundries and creates a first time right environment for PIC designers, PDA brings an additional reduction of development costs by enabling Multi Project Wafer (MPW) runs. In a Multi Project Wafer run, the costs for chip fabrication, masks and set-up time are shared between multiple users. This significantly reduces the barrier to photonic integration and allows photonic chips to be introduced for smaller volume applications than hitherto possible.
Photonics Design Automation as described in this article has been successfully applied to (MPW) runs in InP, TriPleX, as well as silicon photonics technologies. Moreover, the effective use of PDA in well over 100 designs using six different foundries and two packaging providers in less than a year demonstrates that photonics can indeed greatly benefit from leveraging these automation tools. Note that PDA is not only indispensable for photonic foundries, the same approach can be just as beneficial for an in-house wafer fab. The PDA framework also allows third parties to develop versatile libraries of building blocks or to introduce convenient plug-ins, such as the two Arrayed Waveguide Grating plug-ins that were actively used in the above mentioned MPW runs.
The biggest immediate benefit from deploying reusable building blocks in stable and mature processes, independent of whether it’s in a commercial foundry or an in-house fab, is that it improves yield and significantly brings down the costs of the chips as well as the associated development. This in itself is huge, because there are many applications, such as FTTH or data warehousing, where many millions of photonic chips can be deployed, but where the cost of optics has often still proven to be a barrier. But beyond bringing down the costs for high-volume applications, Photonics Design Automation also allows photonic chips to be introduced to a wider audience. There any many applications such as in bioscience, defense and fiber sensing, where volumes are smaller but that could benefit enormously from using integrated photonic chips. And PDA may just be the tool that now brings within reach those lower volume, but equally important, applications.
- Photonic Design Kits: PhoeniX Software
- M.K. Smit et al: ‘Generic foundry model for InP-based photonics,’ IET Optoelectronics, Vol 5(2011), No. 5, p. 187-194
- InP MPW brokering organisation: JePPIX
- TriPleX foundry: LioniX
- SOI MPW brokering organisation: ePIXfab