A new technology delivers temperature hardening in a number of products at the CMOS process level while increasing overall product reliability and longevity. Providing solutions that operate successfully in extreme temperature applications in the oil and gas, space, automotive, aerospace, and medical industries, as well as broader applications like industrial automation and high-performance computing, is paramount. As a result of the technology, system engineers are able to extend the limits of what’s possible in designing ruggedized and broader electronics for today’s extreme and difficult environments.
The methods used to achieve this increased performance optimize process, layout, and circuit design parameters. The implementation of a Buried Guard Ring (BGR) and implant layer adjustments significantly drops the parasitic NPN base resistance (resistance to ground) to prevent the intrinsic base voltage to rise enough to forward bias to the parasitic NPN e-b junction. These implants are completed without damaging or creating defects in the silicon.
These techniques have been applied to SRAM memories, DSPs, and a System on Chip (SOC) based on an ARM® Cortex® M0 microprocessor. The microprocessor and SRAM have been tested with clock rates up to 70 MHz and at temperatures up to 250 C. Both parts have performed without error or latch-up under these conditions. For example, the 132-milliontransistor 18-Mb SBRAM has average core leakage current of 190 mA at a temperature of 200 °C with a core voltage of 1.5V.
As part of the life test, temperature cycling was intentionally induced to add stress to the device. The temperature cycle started with a 20-minute ramp from 25 °C to 250 °C at 30 MHz. The device was continuously tested under the same pattern conditions for 8 hours at 250 °C before being ramped down to 25 °C and the test cycle repeated. Continuous validation of the full address space was performed. Current sigma throughout the life test was less than 1% when compensated for variations in the temperature. No errors or latch-ups have been logged, and no degradation or variability in performance has occurred over the duration of the test. This test has been running for over 2,500 hours, which corresponds to more than 100 trillion bit reads without an error.
This work was done by Brad Ostman of Silicon Space Technology. For more information, Click Here.