The I2C/SPI Verilog core consists of a combined register transfer logic (RTL) Verilog code for a general-purpose I2C and serial-to-parallel interface (SPI) slave for implementations targeting field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs). The core was developed as part of the radiation hardened digital-to-analog converters’ 10-bit (RH-DAC10) and 12-bit (RH-DAC12) ASICs. The core contains both an I2C and SPI slave cores that share all inputs/outputs, and is selectable by setting a single input. The I2C portion uses an asynchronous design and does not require a continuous clock to operate, thus reducing the dynamic power consumption. The core serves as a baseline that can be tailored to any application requiring I2C and SPI slave interfaces. The core has been implemented and verified in both a commercial FPGA and a custom, radiation-hardened ASIC in a commercial CMOS (complementary metal-oxide semiconductor) 0.25-μm process, where the I2C and SPI were tested at 1 MHz and 50 MHz, respectively.

The innovation features plug-and-play capability with minimal modification, is pin/port selectable, and clock and data input is shared between I2C and SPI logic. The I2C address bits are shared with SPI chip select (CS), serial-data-output (SDO), and serial load (SLD). The I2C uses an asynchronous clock to reduce dynamic power consumption, and can use active pull-down for tri-state buffers for data signals. Other features include single/shared active low reset for both cores.

This work was done by George Suarez, Jeffrey DuMonthier, and George Winkert of Goddard Space Flight Center. GSC-16978-1


NASA Tech Briefs Magazine

This article first appeared in the December, 2015 issue of NASA Tech Briefs Magazine.

Read more articles from this issue here.

Read more articles from the archives here.