The EXPRESS Logistics Carrier (ELC) system was built by NASA Goddard for installation on the International Space Station (ISS). Four ELC systems are on ISS. Each ELC site includes two data nodes. The ELC requirements call for a radiation-hardened 10BASE-T Ethernet interface at each data node. The requirement for ELC was to support a full receive version of the interface, and only to provide a link pulse to the attached payloads on the transmit side of the interface. Further development required a full duplex version of a radiation-hardened 10BASE-T Ethernet interface to support the SpaceCube program.

A radiation-hardened 10BASE-T Ethernet solution suitable for spaceflight was developed to meet the requirements set forth by EXPRESS Logistics Carrier and the SpaceCube program. The Ethernet solution has been tested to verify compliance with the Ethernet industry standard IEEE 802.3. This circuit is operating in the ELC avionics system, which is installed on the ISS. A full-duplex (bidirectional) version is also operating on the SpaceCube v1.0 high-performance computing system, which interfaces with ELC on ISS. The SpaceCube v2.0 system is implementing this 10BASE-T Ethernet interface for the Robotics Refueling Mission Phase 3 avionics that will be installed on ISS in 2017. Also, this technology is being used by Moog Broad Reach for use in the Neutron star Interior Composition ExploreR (NICER) ISS payload avionics ( nicer/nicer_about.html).

This innovation combines a custom circuit in conjunction with a front-end field programmable gate array (FPGA) design to implement an Ethernet Physical Interface (PHY) in compliance with IEEE 802.3. The custom circuit makes use of available radiation-hardened parts, and handles the electrical interface between standard differential Ethernet signals and the digital signal levels in the FPGA. The portion of the PHY in the FPGA handles meeting the IEEE 802.3 protocol. It is responsible for decoding received packets and link pulses, and encoding transmitted data packets. Decoded payload data is sent to a user interface (internal to the FPGA). The user interface sends data for transmission back to the FPGA PHY.

The circuit’s transmit portion is comprised of two AD844 op amps from Analog Devices with appropriate filtering. The op amps are tuned to amplify and filter the differential data sent from the FPGA to meet the signal levels and speeds required by Ethernet. The positive and negative portions of the two op amps are then sent through a transformer, which connects to the Ethernet media. The signal returns to an idle level when data stops switching on the data from the FPGA.

The receive portion is comprised of a transformer, an Aeroflex low-voltage differential multi-drop (LVDM) device, and appropriate filtering. The receive pairs are fed from the Ethernet media through the transformer. This data is attenuated to meet its input requirements of the LVDM device, which supports high-speed switching. A single output is driven to the FPGA PHY. On the receive side, in order to meet the idle signal level requirement, the receive polarity needs to be swapped at the input, and then inverted in the FPGA before being processed by the FPGA PHY. This is due to how the LVDM defaults when the input differential voltage is below the specified minimum.

This work was done by Michael Lin, Kevin Ballou, David Petrick, Daniel Espinosa, and Edward James of Goddard Space Flight Center; and Matthew Kliesner of Advanced Optical Systems Inc. GSC-16902-1