Partial bitstream relocation (PBR) on field programmable gate arrays (FPGAs) is a technique to re-scale parallelism of accelerator architectures at run time and enhance fault tolerance. PBR techniques have focused on reading inactive bitstreams stored in memory, on-chip or off-chip, whose contents are generated for a specific partial reconfiguration region (PRR) and modified on demand for configuration into a PRR at a different location.

An alternative to this technique is a PRR-PRR relocation method to generate source and destination addresses, read the bitstream from an active PRR (source) in a nonintrusive manner, and write it to a destination PRR. A hardware-based accelerated relocation circuit (ARC) and a software solution executed on Microblaze were developed on Xilinx Virtex 4 FPGAs.

The ARC consists of three main components: the FAR generator, relocator, and internal communications access port (ICAP) wrapper. The softwarebased approach uses an embedded processor (Microblaze) to transform the relocatable bitstream.

The ARC can relocate frame data bits from one PRR to any other PRR as long as the underlying fabric device primitives are identical. The PRR-PRR relocation technique reads frame data (not the entire bitstream) directly from an active PRR and relocates it to a destination PRR on the fly, accelerating the relocation and removing the need to store any temporary copies of bitstreams.

This work was done by Ramachandra Kallam and Aravind Dasu of Utah State University for Goddard Space Flight Center. GSC-16871-1

NASA Tech Briefs Magazine

This article first appeared in the January, 2016 issue of NASA Tech Briefs Magazine.

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