The University of California Los Angeles (UCLA) has developed a wide range of CMOS (complementary metal–oxide–semiconductor) phase lock loop (PLL) chips with self-healing/self-calibration capabilities, allowing them to adapt, on the fly, to changes in temperature and other environment parameters. All CMOS PLLs typically have three major settings that self-healing and calibration can adjust: VCO (voltage controlled oscillator) coarse tuning, divider tuning, and CML (current mode logic) tuning. Previous work done at UCLA uses these “knobs” or settings exclusively to self-lock a PLL. Locking criteria is established by monitoring the control voltage with an analog-to-digital converter (ADC) to see if the PLL loop is settled in the middle of the range (locked), or sitting at the ground or supply (unlocked).
UCLA delivered such a PLL chip to NASA, and upon delivery, the JPL team made modifications to this existing algorithm to also tune the power amplifier as part of the optimization loop. While not intuitive, the Miller effect of the power amplifier (PA) stage following the PLL can be exploited to extend the frequency lock range of the PLL, and allow it to adapt to a wider range of conditions.
The new software adjusts the output amplifier bias settings of the PLL along with the VCO and dividers in a process called Miller Jogging, which uses the inducted Miller effect properties of the amplifier to influence the lock range of the driving synthesizer. Modern CMOS PLLs have too many settings to exhaustively search all configurations to achieve lock. Sometimes there is difficulty finding lock with only VCO, divider, and CML settings, so searching a wider variable space by adding the power amplifier bias and Miller effect improves robustness of the PLL loop.
This algorithm is highly hardware-dependent and applicable specifically to mm-wave PAs with the correct calibration and lock monitoring hardware included. The algorithm allows the PLL chip to automatically re-calibrate itself for environmental changes. This is very important for planetary missions where temperatures and radiation can cause changes inside the chip.