The International Space Station (ISS) uses a fiber optic High Rate Data Link (HRDL) standard for transferring data. ISS experiments, however, may prefer an Ethernet interface. This design allows ISS instruments to keep their Ethernet interface by converting the Ethernet data format into a format compatible with the ISS. The Express Logistics Carrier (ELC) incorporated this design on the ISS in 2010. The design was described with VHDL code. It has been implemented with an Actel RTAX Field Programmable Gate Array (FPGA). This FPGA is part of the Express Logics Carrier (ELC) onboard the ISS.

The HRDL conversion block consists of an Ethernet interface that monitors the upper four bits of a 68-bit bus for the number of valid bytes and last-word indicator, and converts a 64-bit input bus to 8-bit output.
The HRDL conversion block (see figure) consists of an Ethernet Interface Block that monitors the upper four bits of a 68-bit bus for the number of valid bytes and last-word indicator, and converts a 64-bit input bus to 8-bit output. A Sync Calculator finds the minimum number of required sync markers between frames. A Traffic Cop monitors packet-ready signals to know when RAMs have at least one complete packet. RAM Interface Control communicates with the Ethernet Interface, receives read requests from the Traffic Cop, and interfaces to all SRAM signals.

The 4B/5B Encode converts 4-bit data into 5-bit symbols; the Traffic Cop tells 4B/5B what the output should be. A Parallel-to-Serial/PN7 Test Generator is a 5-bit parallel-to-serial converter and a test pattern for Ethernet transmit. The Test Generator allows for compliance testing when a real data source is not present. The PCI Interface uses local addresses, data buses, and enables generated elsewhere in the FPGA from the PCI bus.

Previous HRDL interfaces on the ISS did not have an Ethernet input. This design works at full HRDL data rates, which requires a 125-MHz high-speed clock. The design can accommodate dual Ethernet inputs multiplexed into a single HRDL stream. Software routines were written to generate Ethernet frames as an input for hardware simulation, as well as routines to analyze HRDL frames from the output of the simulations.

This work was done by Thomas Flatley, Thomas Winkert, Jacqueline LeMoigne-Stewart, and Victor Bigio of Goddard Space Flight Center. NASA is seeking partners to further develop this technology through joint cooperative research and development. For more information about this technology and to explore opportunities, please contact This email address is being protected from spambots. You need JavaScript enabled to view it.. GSC-16513-1

NASA Tech Briefs Magazine

This article first appeared in the May, 2016 issue of NASA Tech Briefs Magazine.

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