The invention is a design for a peripheral component interconnect (PCI) local bus controller and target in a PC/104-Plus form-factor. The design uses a flash-based field programmable gate array (FPGA) to provide immediate functionality from power-on to avoid delay after power is applied. It can be reprogrammed from connectors directly on the board, and is able to both receive and drive the clock for system and local peripherals, allowing it to function as either a PCI bus host controller or PCI target device interface. Fully compliant with the PC/104-Plus specification, the design has associated schematics and Gerber files in a vendor-ready state. The design was developed to support ongoing research in fault-tolerant computing systems.

The hardware assembly hosts flash-based FPGAs, SRAMs, I/O interfaces, and clocking circuitry.

The PCI assembly design supports multiple functions within a computer system. The design hosts flash-based FPGAs, SRAMs, I/O interfaces, and clocking circuitry. The circuit accommodates in-system programming via onboard connectors, and allows functionality with separate hardware implementations with controller functionality or add-on-card functionality. Potential applications include fault-tolerant computing systems, high-speed data acquisition, video acquisition, surveillance, communication gateway routers, embedded servers, and intelligent transportation systems.

NASA is actively seeking licensees to commercialize this technology. Please contact The Technology Gateway at This email address is being protected from spambots. You need JavaScript enabled to view it.to initiate licensing discussions. Follow this link for more information: https://technology.nasa.gov/patent/TB2016/LAR-TOPS-149.