would be capable of real-time, onboard processing of complete sets of interferometric radar data is undergoing development. Intended for original use as part of a spaceborne interferometric radar system, this data-processing system or parts of it could be adapted to diverse other remote-sensing systems, including spaceborne and airborne synthetic- aperture radar systems, radar altimeters, and collision-avoidance radar systems.

Heretofore, the large amount of data and large number of arithmetic operations required by interferometric-radar algorithms have made it necessary to either downlink the data for postprocessing or else limit collection of data and thereby limit spatial coverage. The present developmental system would make it unnecessary to compromise between spatial coverage and real-time processing and, by performing high data rate processing onboard, would reduce the volume of data to be ultimately downlinked.

The architecture of this system is based partly on a fast-convolution processing engine (for chirp-radar pulse compression) that is capable of receiving processing-parameter updates dynamically via a low-bandwidth interface from a separate onboard computer (OBC). The fast-convolution processing engine and associated processing subsystems constitute an ultrafast digital processor implemented in hardware as a specialized field-programmable gate array (FPGA) containing 3 million gates with a clock running at a speed of 60 MHz. The parameter-update mechanism makes it possible to perform sophisticated mathematical corrections on-chip for range migration and wavenumber shift, both of which would otherwise introduce unacceptable correlation errors into the processed interferometric radar data.

A major feature of the architecture of this system is optimal partitioning of the radar processing functions between (1) ultrafast processing in hardware (that is, in the FPGA) and (2) slower but more adaptable software-controlled processing in the OBC. Another major feature is provision of a simple, low-bandwidth interface through which the OBC dynamically updates several parameters in the FPGA processing engine in real time. In this architecture, algorithmically complex operations are performed in the OBC, while repetitive linear operations are parameterized and performed within the FPGA.

The convolution processor performs fast frequency-domain pulse-compression: The incoming data are first subjected to a fast Fourier transform (FFT), the transform data are multiplied by a matched reference function, then the resulting data are subjected to an inverse FFT. The convolution processor is instantiated twice in the FPGA logic, once for each of two interferometric channels.

To perform all the convolution processing functions, it is necessary to run the radar-return data through multiple passes of a single, specialized processing cell. The hardware in this cell (see figure) includes a reorder memory bank, a radix-16 Winograd FFT kernel, a coordinate- rotation digital computer (CORDIC) phase rotator, and a complex multiplier. The pulse-compression operation is essentially decomposed into eight passes per pulse-repetition interval: one pass for putting the input data into memory, three passes for the forward FFT and multiplication by the reference function, three passes for the inverse FFT, and one pass for reordering the output data into their natural sequence.

An innovative aspect of this system is that the CORDIC input argument can be multiplexed to on-chip phase-generation logic circuitry during the third forward- FFT pass and the third inverse-FFT pass. This makes it possible to effect a time-varying delay (to apply time shifts for range-migration corrections and electronic beam steering) by applying a linear phase ramp to the frequency-domain data during the third forward-FFT pass. Likewise, a frequency shift (to align the spectra between the two channels to correct for wave-number shift) can be effected by applying a phase ramp to the pulse-compressed data during the third inverse-FFT pass.

The phase-generation circuitry within the FPGA takes, as its input, parameter values for calculating the slope and the offset of the frequency and time-domain phase ramps. These parameter values are precisely computed and updated by the OBC (on the basis of the current position of the satellite or other radar platform along its trajectory) to registers within the processor FPGA approximately once per second. This processing cell structure thereby enables very precise correction of the received radar data in real time before data from the two channels of the interferometer are cross-multiplied in hardware to form the interferogram. The corrections are expected to afford centimeter-level accuracy and precision in the retrieval of such geophysical parameters as sea surface height.

This work was done by Mark Fischman and Marc Simard of Caltech for NASA's Jet Propulsion Laboratory and Raymond Andraka of Andraka Consulting Group, Inc. For further information, access the Technical Support Package (TSP) free on-line at www.techbriefs.com/tsp under the Electronics/ Computers category.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to:

Innovative Technology Assets Management
Mail Stop 202-233
4800 Oak Grove Drive
Pasadena, CA 91109-8099
(818) 354-2240
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Refer to NPO-42026, volume and number of this NASA Tech Briefs issue, and the page number.

This Brief includes a Technical Support Package (TSP).
Ultrafast Processor for Interferometric Radar

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This article first appeared in the March, 2006 issue of NASA Tech Briefs Magazine.

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