Interdigital overlay capacitors have been invented to decrease the amount of integrated-circuit chip area needed to accommodate a given amount of capacitance. In most very-large-scale integrated (VLSI) circuits and monolithic microwave integrated circuits (MMIC), the integrated capacitors are the largest circuit elements. By making it possible to fit the capacitors within smaller chip areas, this invention offers the potential to reduce the overall chip sizes, increase the numbers of circuit elements that can be accommodated on given chip areas, and/or satisfy increasingly stringent design constraints on the dimensions of circuit elements.

Figure 1. Layers of Metal and Dielectric Material are stacked in alternation, and the metal electrodes are connected alternately to two terminals to form a multilayer capacitor.

An interdigital overlay capacitor is a multilayer parallel-plate capacitor with thin layers of dielectric material between the electrodes. It is so named because its electrodes appear interdigitated in a cross-sectional view (see Figure 1) and because its layers are stacked or overlaid on an integrated-circuit chip. The chip area occupied by an interdigital overlay capacitor is the same as that of a conventional dielectric-overlay capacitor, which contains only one dielectric layer and thus has less capacitance.

Figure 2. Measurements of Capacitance (C) vs. Overlapping Electrode Area (A) have been fitted with a straight line represented by the equation C = 4.4¥ 104A + 3.35. The 3.35 pF is a fringing capacitance.

Prototype interdigitated overlay capacitors have been made by use of established integrated-circuit fabrication techniques: The metal electrode layers were made by evaporative deposition of Ti sublayers to a thickness of 300 Å and Au sublayers to a thickness of 2,000 Å. The dielectric layers were made by deposition of a nitride material deposited from a room-temperature electron-cyclotron-resonance plasma, with patterning by a lift-off photolithographic process. The relative permittivity of the dielectric layers was =6, and the thickness of each dielectric layer was about 1,200 Å. To provide a taper needed to ensure a high yield of the fabrication process, each metal layer in a stack was recessed from the one below it by a margin of 5 *m.

Figure 2 is a plot of measured capacitances of prototype one-, two-, and three-layer interdigitated overlay capacitors versus overlapping electrode area. These measurements show that the capacitance was doubled from 9 pF (for one layer) to 18 pF (for three layers) without increasing the capacitor base area.

This work was done by Trong-Huang Lee, Jeff Hong, and Imran Mehdi of Caltech for NASA's Jet Propulsion Laboratory.

In accordance with Public Law 96-517, the contractor has elected to retain title to this invention. Inquiries concerning rights for its commercial use should be addressed to

Technology Reporting Office
JPL
Mail Stop 122-116
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Pasadena, CA 91109
(818) 354-2240

Refer to NPO-20383